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| mas 3587f mpeg layer 3 audio encoder/decoder edition march 2, 2001 6251-542-1ai advance information micr onas micronas
mas 3587f advance information 2 micronas contents page section title 5 1. introduction 5 1.1. features 6 1.2. application overview 7 2. functional description of the mas 3587f 72.1.overview 7 2.2. architecture of the mas 3587f 7 2.3. dsp core 7 2.4. ram and registers 8 2.5. firmware and software 8 2.5.1. internal program rom and firmware, mpeg-encoding/decoding 9 2.5.2. program download feature 9 2.6. audio codec 9 2.7. a/d converter and microphone amplifier 9 2.7.1. baseband processing 9 2.7.1.1. bass, treble, and loudness 9 2.7.2. micronas dynamic bass (mdb) 9 2.7.2.1. automatic volume control (avc) 10 2.7.2.2. balance and volume 10 2.7.3. d/a converters 10 2.7.4. output amplifiers 10 2.8. clock management 11 2.8.1. dsp clock 11 2.8.2. clock output at clko 11 2.9. power supply concept 11 2.9.1. power supply regions 11 2.9.2. dc/dc converters 13 2.9.3. power supply configurations 13 2.10. battery voltage supervision 14 2.11. interfaces 14 2.11.1. i 2 c control interface 14 2.11.2. s/pdif input interface 14 2.11.3. s/pdif output 14 2.11.4. multiline serial audio input (sdi, sdib) 14 2.11.5. multiline serial output (sdo) 14 2.11.6. parallel input/output interface (pio) 15 2.12. mpeg synchronization output 15 2.13. default operation 15 2.13.1. stand-by functions 15 2.13.2. power-up of the dc/dc converters and reset 16 2.13.3. control of the signal processing 16 2.13.4. start-up of the audio codec 16 2.13.5. power-down contents, continued page section title advance information mas 3587f micronas 3 17 3. i 2 c interface 17 3.1. general 17 3.1.1. device address 17 3.1.2. i 2 c registers and subaddresses 18 3.1.3. naming convention 19 3.2. direct configuration registers 19 3.2.1. write direct configuration registers 19 3.2.2. read direct configuration register 24 3.3. dsp core 24 3.3.1. access protocol 25 3.3.1.1. run and freeze 25 3.3.1.2. read register (code a hex ) 26 3.3.1.3. write register (code b hex ) 26 3.3.1.4. read d0 memory (code c hex ) 27 3.3.1.5. short read d0 memory (code c4 hex ) 27 3.3.1.6. read d1 memory (code d hex ) 28 3.3.1.7. short read d1 memory (code d4 hex ) 28 3.3.1.8. write d0 memory (code e hex ) 29 3.3.1.9. short write d0 memory (code e4 hex ) 29 3.3.1.10. write d1 memory (code f hex ) 29 3.3.1.11. short write d1 memory (code f4 hex ) 30 3.3.1.12. clear sync signal (code 5 hex ) 30 3.3.1.13. default read 31 3.3.1.14. fast program download 31 3.3.1.15. serial program download 32 3.3.2. list of dsp registers 32 3.3.3. list of dsp memory cells 32 3.3.3.1. application select and running 32 3.3.3.2. application specific control 40 3.3.4. ancillary data 41 3.3.5. dsp volume control 42 3.4. audio codec access protocol 42 3.4.1. write codec register 42 3.4.2. read codec register 43 3.4.3. codec registers 49 3.4.4. basic mdb configuration 50 4. specifications 50 4.1. outline dimensions 50 4.2. pin connections and short descriptions 53 4.3. pin descriptions 53 4.3.1. power supply pins 53 4.3.2. analog reference pins 53 4.3.3. dc/dc converters and battery voltage supervision 53 4.3.4. oscillator pins and clocking 53 4.3.5. control lines 53 4.3.6. parallel interface lines mas 3587f advance information 4 micronas contents, continued page section title 54 4.3.6.1. pio handshake lines 54 4.3.7. serial input interface (sdi) 54 4.3.8. serial input interface b (sdib) 54 4.3.9. serial output interface (sdo) 54 4.3.10. s/pdif input interface 54 4.3.11. s/pdif output interface 54 4.3.12. analog input interfaces 54 4.3.13. analog output interfaces 55 4.3.14. miscellaneous 55 4.4. pin configurations 56 4.5. internal pin circuits 58 4.6. electrical characteristics 58 4.6.1. absolute maximum ratings 59 4.6.2. recommended operating conditions 62 4.6.3. digital characteristics 63 4.6.3.1. i 2 c characteristics 64 4.6.3.2. serial (i 2 s) input interface characteristics (sdi, sdib) 66 4.6.3.3. serial output interface characteristics (sdo) 68 4.6.3.4. s/pdif input characteristics 69 4.6.3.5. s/pdif output characteristics 70 4.6.3.6. pio as parallel input interface: dma mode 71 4.6.3.7. pio as parallel output interface: dma mode 72 4.6.4. analog characteristics 76 4.6.5. dc/dc converter characteristics 77 4.6.6. typical performance characteristics 79 4.7. typical application in a portable player 80 4.8. recommended dc/dc converter application circuit 82 5. data sheet history advance information mas 3587f micronas 5 mpeg layer 3 audio encoder/decoder this data sheet applies to mas 3587f version a1. 1. introduction the mas 3587f is a single-chip mpeg layer 3 audio encoder/decoder designed for use in memory-based recording/playback applications, e.g. mp3 record/play- back equipment. the ic contains a dsp engine with embedded ram and rom. it provides flexible digital interfaces for serial and s/pdif audio data input and output. also integrated are power management func- tions and two dc/dc converters for single cell power supply. a high-quality stereo d/a converter and a ste- reo a/d converter on chip provide the analog functions required in an advanced portable audio player. in encoding mode, audio data is input via the inte- grated a/d converter, serial pcm, or s/pdif interface. the compressed digital data stream is sent via the par- allel interface. in decoding mode, compressed digital data streams are accepted in the parallel or serial for- mat. the audio data is output via the high quality d/a converter. a digital output in serial pcm format and/or s/pdif format is also provided. thus, the mas 3587f provides a true ?all-in-one? solution that is ideally suited for highly optimized mem- ory based music recorders. additional functionality is achieved via download soft- ware (e.g. micronas sc4 encoder/decoder). sc4 is a proprietary micronas speech codec technology based on adpcm. the codec can be downloaded to the mas 3587f to allow high quality speech recording and playing back at various sampling rates. (please con- tact your local micronas sales representative about availability of sc4 downloads). in mpeg 1 (iso 11172-3), three hierarchical layers of compression have been standardized. the most sophisticated and complex, layer 3, allows compres- sion rates of approximately 12:1 for mono and stereo signals while still maintaining cd audio quality. 1.1. features firmware ? mpeg 1/2 layer 3 encoder ? encoding with adaptive bit rate up to max. 192 kbit/s ? mpeg 1/2 layer 2 and layer 3 decoder ? decoder-extension to mpeg 2 layer 3 for low bit rates (?mpeg 2.5?) ? extraction of mpeg ancillary data ? adaptive bit rates (bit rate switching) ? sdmi-compliant security technology for decoder ? stereo channel mixer ? bass, treble and loudness function ? micronas dynamic bass (mdb) ? automatic volume control (avc) interfaces ? 2 serial asynchronous interfaces for bitstreams and uncompressed digital audio ? parallel handshake bit stream input/output ? serial audio output via i 2 s and related formats ? s/pdif audio input ? s/pdif audio output ? controlling via i 2 c interface hardware features ? two independent embedded dc/dc converters (e.g. for dsp and flash ram supply) ? low dc/dc converter start-up voltage (0.9 v) ? dc converter efficiency up to 95 % ? battery voltage monitor ? low supply voltage (down to 2.2 v for decoder, 3.5 v for encoder) ? low power dissipation (<70 mw for decoder, <400 mw for encoder) ? hardware power management and power-off func- tions ? microphone amplifier ? stereo a/d converter for fm/am-radio and speech input ? cd quality stereo d/a converter ? headphone amplifier ? on-chip crystal oscillator ? external clock or crystal frequency of 13...20 mhz ? standby current < 10 a mas 3587f advance information 6 micronas 1.2. application overview the following block diagram shows an example appli- cation for the mas 3587f in a portable audio recorder device. besides a simple controller and the external flash memories, all required components are inte- grated in the mas 3587f. by means of the embedded a/d-converter, the mas 3587f supports both speech and fm radio quality audio encoding. cd-quality encoding/decoding is achieved by using digital inputs/ embedded d/a-converter. fig. 1 ? 1 depicts a portable audio application that is power optimized. the two embedded dc/dc convert- ers of the mas 3587f generate optimum power supply voltages for the dsp core and also for state-of-the art flash memories that typically require 2.7 to 3.3 v sup- ply. the performance of the dc/dc converters reaches efficiencies up to 95%. fig. 1?1: example application for the mas 3587f in a portable audio recorder device a/d microphone amplifier d/a headphone amplifier volume line in optional digital in s/pdif or serial crystal osc./pll dc/dc1 i 2 c dc/dc2 audio baseband features mp3 encoding/ headphone digital out s/pdif or serial system clock e.g. 2.7 v e.g. 3.5 v / i 2 c control parallel i/o bus i 2 c flash ram c display keyboard pc connector decoding optional software downloads 2.2 v advance information mas 3587f micronas 7 2. functional description of the mas 3587f 2.1. overview the mas 3587f is intended for use in consumer audio applications. it encodes analog audio input, pcm data or s/pdif signals to variable bit rate mpeg 1/2 layer 3 data streams. the compressed data is stored in an external memory via the parallel port. for playback it receives s/pdif, parallel or serial data streams and decodes mpeg layer 2 and 3 (including the low sam- pling frequency extensions). 2.2. architecture of the mas 3587f the hardware of the mas 3587f consists of a high- performance risc digital signal processor (dsp), and appropriate interfaces. a hardware overview of the ic is shown in fig. 2 ? 1. 2.3. dsp core the internal processor is a dedicated dsp for advanced audio applications. 2.4. ram and registers the dsp core has access to two ram banks denoted d0 and d1. all ram addresses can be accessed in a 20-bit or a 16-bit mode via i 2 c bus. for fast access of internal dsp states the processor core has an address space of 256 data registers which can be accessed by i 2 c bus. for more details please refer to section 3.3. on page 24. fig. 2 ? 1: the mas 3587f architecture 2 2 mic. input (incl. bias) line input s/pdif input 1 s/pdif input 2 serial audio (i 2 s, sdi) serial audio (stream, sdib) v bat v1 v2 xtal 18.432 mhz clko parallel i/o bus (pio) i 2 c s/pdif output serial audio (i 2 s, sdo) audio output control alu mac accumulators rom d0 d1 registers div. input select output select a/d audio proc. d/a control dccf dcfr dsp codec volt. mon. i 2 c interface div. scaler osc. pll synth. dc/dc 2 dc/dc 1 synthesizer clock 1 2 2 mix mas 3587f advance information 8 micronas 2.5. firmware and software 2.5.1. internal program rom and firmware, mpeg-encoding/decoding the firmware implemented in the program rom of the mas 3587f provides mpeg 1/2 layer 3 encoding and decoding of mpeg 1/2 layer 2 and mpeg 1/2 layer 3. the dsp operating system starts the firmware in the ? application selection mode ? . by setting the appropri- ate bit in the application select memory cell (see ta b l e 3 ? 6 on page 33), the mpeg audio encoder or decoder can be activated. the mpeg decoder provides an automatic standard detection mode. if all mpeg audio decoders are selected, the layer 2 or layer 3 bitstream is recog- nized and decoded automatically. for general control purposes, the operation system provides a set of i 2 c instructions that give access to internal dsp registers and memory areas. an auxiliary digital volume control and mixer matrix is applied to the digital stereo audio data. this matrix is capable of performing the balance control and a simple kind of stereo basewidth enhancement. all four factors ll, lr, rl, and rr are adjustable, please refer to fig. 3 ? 3 on page 41. fig. 2 ? 2: encoder signal flow fig. 2 ? 3: decoder signal flow out a/d audio proc. d/a encoder mix sdo s/pdif pio s/pdif s/pdif2 sdi line in mic in out a/d audio proc. d/a decoder mix sdo s/pdif pio sdib line in dsp volume matrix mic in advance information mas 3587f micronas 9 2.5.2. program download feature the standard functions of the mas 3587f can be extended or substituted by downloading up to 4kwords (1 word = 20 bits) of program code and additionally up to 4kwords of coefficients into the internal ram. the code must be downloaded by the fast program download command (see section 3.3.1.14. on page 31) into an area of ram that is switchable from data memory to program memory. a run command (see section 3.3.1.1. on page 25) starts the operation. 2.6. audio codec a sophisticated set of audio converters and sound fea- tures has been implemented to comply with various kinds of operating environments that range up to high- end equipment (see fig. 2 ? 4). fig. 2 ? 4: signal flow block diagram of audio codec 2.7. a/d converter and microphone amplifier a pair of a/d converters is provided for recording or loop-through purposes. in addition, a microphone amplifier including voltage supply function for an elec- tret type microphone has been integrated. 2.7.1. baseband processing the several baseband functions are applied to the dig- ital audio signal immediately before d/a conversion. 2.7.1.1. bass, treble, and loudness standard baseband functions such as bass, treble, and loudness are provided (refer to table 3 ? 12 on page 43 for details). 2.7.2. micronas dynamic bass (mdb) the micronas dynamic bass system (mdb) was developed to extend the frequency range of loud- speakers or headphones below the cutoff frequency of the speakers. in addition to dynamically amplifying the low frequency bass signals, the mdb exploits the psy- choacoustic phenomenon of the ? missing fundamen- tal ? . adding harmonics of the frequency components below the cutoff frequency gives the impression of actually hearing the low frequency fundamental, while at the same time retaining the loudness of the original signal. due to the parametric implementation of the mdb, it can be customized to create different bass effects and adapted to various loudspeaker character- istics (see section 3.4.4. on page 49). 2.7.2.1. automatic volume control (avc) in a collection of tracks from different sources fairly often the average volume level varies. especially in a noisy listening environment the user must adjust the volume to achieve a comfortable listening enjoyment. the automatic volume correction (avc) solves this problem by equalizing the volume level. to prevent clipping, the avc's gain decreases quickly in dynamic boost conditions. to suppress oscillation effects, the gain increases rather slowly for low level inputs. the decay time is programmable by means of the avc register (see table 3 ? 12 on page 43). for input levels of -18 dbr to 0 dbr, the avc maintains a fixed output level of -9 dbr. fig. 2 ? 5 shows the avc output level versus its input level. for volume and baseband registers set to 0 db, a level of 0 dbr corre- sponds to full scale input/output. fig. 2 ? 5: simplified avc characteristics mic-in a d a d line-in deemphasis mono 50s / 75s mixer mono/stereo avc bass/treble loudness right invert a d a d volume balance audio codec mic-amplifier incl. bias dsp output mdb headphone amplifier q-peak q-peak 30 24 18 12 6 6 input level 15 21 9 output level dbr dbr 0 off on mas 3587f advance information 10 micronas 2.7.2.2. balance and volume to minimize quantization noise, the main volume con- trol is automatically split into a digital and an analog part. the volume range is ? 114...+12 db with an addi- tional mute position. a balance function is provided (see table 3 ? 12 on page 43). 2.7.3. d/a converters a pair of micronas ? unique multibit sigma-delta d/a converters is used to convert the audio data with high linearity and a superior s/n. in order to attenuate high- frequency noise caused by noise-shaping, internal low-pass filters are included. they require additional external capacitors between pins filtr and outr, and filtl and outl respectively (see section 4.7. on page 79). 2.7.4. output amplifiers the integrated output amplifiers are capable of driving stereo headphones of 16...32 ? impedance via 22- ? series resistors or built-in loudspeakers of 16 ? imped- ance directly. if more output power is required, the right output signal can be inverted and a single loudspeaker can be connected as a bridge between pins outl and outr. in this case the minimum impedance is 32 w, and for optimized power the source should be set to mono. fig. 2 ? 6: bridge operation mode 2.8. clock management the mas 3587f is driven by a single crystal-controlled clock with a frequency of 18.432 mhz. it is possible to drive the mas 3587f with other reference clocks. in this case, the nominal crystal frequency must be writ- ten into memory location d0:7f3. the crystal clock acts as a reference for the embedded synthesizer that gen- erates the internal clock. for compressed audio data reception, the mas 3587f may act either as the clock master (demand mode) or as a slave (broadcast mode) as defined by bit 1 in iocontrolmain memory cell (see table 3 ? 7 on page 34). in both modes, the output of the clock syn- thesizer depends on the sample rate of the decoded data stream as shown in table 2 ? 1. in the broadcast mode (pll on), the incoming audio data controls the clock synthesizer via a pll. in the demand mode (pll off) the mas 3587f acts as the system master clock, the internal clock. the data transfer is triggered by a demand signal at pin eod . this mode is used in most applications. in the encoder application, the mas 3587f is clock master in case of i 2 s audio input. for s/pdif input, the mas 3587f synchronizes the clock to the incomming s/pdif signal. r 32 ? masf dac dac outl outr table 2 ? 1: settings of bits 8 and 17 in outclkconfig and resulting clko output frequencies f s /khz output frequency at clko/mhz synth. clock bit 8=1 scaler on bit 8=0, bit 17=0 scaler plus extra division bit 8=0, bit 17=1 48 24.576 512 ? f s 24.576 256 ? f s 12.288 44.1 22.5792 22.5792 11.2896 32 24.576 768 ? f s 24.576 384 ? f s 12.288 24 512 ? f s 12.288 256 ? f s 6.144 22.05 22.5792 11.2896 5.6448 16 24.576 768 ? f s 12.288 384 ? f s 6.144 12 512 ? f s 6.144 256 ? f s 3.072 11.025 22.5792 5.6448 2.8224 8 24.576 768 ? f s 6.144 384 ? f s 3.072 advance information mas 3587f micronas 11 2.8.1. dsp clock the dsp clock has a separate divider. for power con- servation it is set to the lowest acceptable rate of the synthesizer clock which is capable to allow the proces- sor core to perform all tasks. 2.8.2. clock output at clko if the dsp or audio codec functions are enabled (bits 11 or 10 in the control register at i 2 c subaddress 6a hex ), the reference clock at pin clko is derived from the synthesizer clock. dependent on the sample rate of the decoded signal a scaler is applied which automatically divides the clock- out by 1, 2, or 4, as shown in table 2 ? 1. an additional division by 2 may be selected by setting bit 17 of the output clock configuration memory cell, outclkconfig (see table 3 ? 7 on page 34). the scaler can be dis- abled by setting bit 8 of this cell. the controlling at outclkconfig is only possible as long as the dsp is operational (bit 10 of the control register). settings remain valid if the dsp is disabled by clearing bit 10. 2.9. power supply concept the mas 3587f has been designed for minimal power dissipation. in order to optimize the battery manage- ment in portable players, two dc/dc converters have been implemented to supply the complete portable audio player with regulated voltages. 2.9.1. power supply regions the mas 3587f has five power supply regions. the vdd/vss pin pair supplies all digital parts includ- ing the dsp core, the xvdd/xvss pin pair is con- nected to the digital signal pin output buffers, the avdd0/avss0 supply is for the analog output amplifi- ers, avdd1/avss1 for all other analog circuits like clock oscillator, pll circuits, system clock synthesizer and a/d and d/a converters. the i 2 c interface has an own supply region via pin i2cvdd. connecting this to the microcontroller supply assures that the i 2 c bus always works as long as the microcontroller is alive so that the operating modes can be selected. beside these regions, the dc/dc converters have start-up circuits of their own which get their power via pin vsensx. 2.9.2. dc/dc converters the mas 3587f has two embedded high-performance step-up dc/dc converters with synchronous rectifiers to supply both the dsp core itself and external circuitry such as a controller or flash memory at two different voltage levels. an overview is given in fig. 2 ? 7 on page 12. the dc/dc converters are designed to generate an output voltage between 2.0 v and 3.5 v which can be programmed separately for each converter via the i 2 c interface (see table 3 ? 3 on page 20). both converters are of the bootstrapped type which allow start up from a voltage down to 0.9 v for use with a single battery or nicd/nimh cell. the default output voltages are 3.0 v. both converters are enabled with a high level at pin dcen and enabled/disabled by the i 2 c interface. the mas 3587f dc/dc converters feature a constant- frequency, low noise pulse width modulation (pwm) mode and a low quiescent current, pulse frequency modulation (pfm) mode for improved efficiencies at low current loads. both modes ? pwm or pfm ? can be selected independently for each converter via i 2 c interface. the default mode is pwm. in the pwm mode, the switching frequency of the power-mosfet-switches is derived from the crystal oscillator. switching harmonics generated by constant frequency operation are consistent and predictable. when the audio codec is enabled the switching fre- quency of the converters is synchronised to the audio codec clock to avoid interferences into the audio band. the actual switching frequency can be selected via the i 2 c-interface between 300 khz and 580 khz (for details see dcfr register in table 3 ? 3 on page 20). in the pfm operation mode, the switching frequency is controlled by the converters themself, it will be just high enough to service the output load thus resulting in the best possible efficiency at low current loads. pfm mode does not need a clock signal from the crystal oscillator. if both converters do not use the pwm- mode, the crystal clock will be shut down as long it is not needed from other internal blocks. the synchronous rectifier bypasses the external schottky diode to reduce losses caused by the diode forward voltage providing up to 5% efficiency improve- ment. by default, the p-channel synchronous rectifier switch is turned on when the voltage at pin(s) dcson exceeds the converter ? s output voltage at pin(s) vsensn and turns off when the inductor current drops below a threshold. if one or both converters are dis- abled, the corresponding p-channel switch will be turned on, connecting the battery voltage to the dc/ dc converters output voltage at pin vsensn. how- ever, it is possible to individually disable both synchro- nous rectifier switches by setting the corresponding bits (bit 8 and 0 in dccf-register). mas 3587f advance information 12 micronas if both dc/dc-converters are off, a high signal may be applied at pin dcen. this will start the converters in their default mode (pwm with 3.0 v output voltage). the pup signal will change from low to high when both converters have reached their nominal output voltage and will return to low when both converters output volt- ages have dropped 200 mv below their programmed output voltage. the signal at pin pup can be used to control the reset of an external microcontroller (see section 2.13.2. on page 15 for details on start up pro- cedure). if only dc/dc-converter 1 is used, the output of the unused converter 2 (vsens2) must be connected to the output of converter 1 (vsens1) to make the pup signal work properly. also, if a dc/dc-converter is not used (no inductor connected), the pin dcso must be left vacant. fig. 2 ? 7: dc/dc converter overview (dcen input must be connected to pin i2cvdd via the start-up push button) 15 8 ? + ? + vss dcso2 dcsg2 dcen pup vsens2 v in 22 h c1 330 f s r 30 dcfr (77 hex ) dccf (76 hex ) 70 dccf (76 hex ) d1 start pup2 set voltage factor output 1 i2cvdd to i 2 c interface supply l1 vbat battery voltage monitor dc/dc converter 2 voltage monitor voltage monitor dc/dc converter 1 frequency divider system or crystal clock ? + advance information mas 3587f micronas 13 2.9.3. power supply configurations one of the following supply configurations may be used: ? configuration 1: dc/dc 1 (e.g. 2.7 v) supplies con- troller, flash and mas 3587f audio parts, dc/dc 2 generates e.g. 2.5 v/3.5 v for the mas 3587f dsp (see fig. 2 ? 8). ? configuration 2: all components are powered by an external source, no dc/dc converter is used (see fig. 2 ? 9). if dc/dc converter 1 is used, it must supply the analog circuits (pins avdd0, avdd1) of the mas 3587f. if the dc/dc converters are not used, pin dcen must be connected to vss, dcsox must be left vacant. 2.10. battery voltage supervision a battery voltage supervision circuit (at pin vbat) is provided which is independent of the dc/dc convert- ers. it can be programmed to supervise one or two bat- tery cells. the voltage is measured by subsequently setting a series of voltage thresholds and checking the respective comparison result in register 77 hex (see ta b l e 3 ? 3 on page 20). fig. 2 ? 8: configuration1: dc/dc-converter supply fig. 2 ? 9: configuration2: external power supply flash c dsp vsens1 avdd0/1 vsens2 xvdd vdd i 2 cvdd dc/dc1 i 2 c dc/dc2 analog parts e.g. 3.5 v e.g. 2.7 v on on /2.5 v flash c dsp vsens1 avdd0/1 vsens2 vdd xvdd i 2 cvdd dc/dc1 i 2 c dc/dc2 analog parts external supply e.g. 3.5 v/ off off 2.7 v mas 3587f advance information 14 micronas 2.11. interfaces the mas 3587f uses an i 2 c control interface, a paral- lel i/o interface (pio) for mpeg bit streams and digital audio interfaces for the incomming/outgoing audio data (i 2 s or similar). alternatively, spdif input and output interfaces can be used. mpeg bit stream input to the decoder is also possible via a second serial input interface. 2.11.1. i 2 c control interface for controlling and program download purposes, a standard i 2 c slave interface is implemented. a detailed description of all functions can be found in section 3. 2.11.2. s/pdif input interface the s/pdif interface receives a one-wire serial bus signal. in addition to the signal input pin spdi1/spdi2, a reference pin spdir is provided to support balanced signal sources or twisted pair transmission lines. the synchronization time on the input signal is <50ms. the spdif input signal can also be switched to the spdo pin. in this case the analog input circuit of the spdif inputs (see fig. 4 ? 16 on page 57) restores the spdif input signal to a full swing signal at spdo. for controlling details please refer to table 3 ? 7 on page 34. 2.11.3. s/pdif output the s/pdif output of the baseband audio signals is provided at pin spdo. note that the s/pdif output is available only for mpeg 1 sampling frequencies (32, 44.1, 48 khz). 2.11.4. multiline serial audio input (sdi, sdib) there are two multiline serial audio input interfaces (sdi, sdib) each consisting of the three pins sic, sii, sid, and sibc, sibi, sibd. the firmware supports sdi for audio signals and sdib for bitstream signals. the interfaces can be configured as continuous bit stream or word-oriented inputs. for the mpeg bit- streams the word strobe pin sibi must always be con- nected to v ss , bits must be sent msb first as created by the encoder. during enabling the dsp and its inter- faces, it is strongly recommended to hold the sibc pin low. in case of the demand mode in decoding applications (see section 2.8.), the signal clock coming from the data source must be higher than the nominal data transmission rate (e.g. 128 kbit/s). pin eod is used to interrupt the data flow whenever the input buffer of the mas 3587f is filled. for controlling details please refer to table 3 ? 7 on page 34. 2.11.5. multiline serial output (sdo) the serial audio output interface of the mas 3587f is a standard i 2 s-like interface consisting of the data lines sod, the word strobe soi and the clock signal soc. it is possible to choose between two standard interface configurations (16-bit data words with word strobe time offset or 32-bit data words with inverted soi-signal). if the serial output generates 32 bits per audio sample, only the first 20 bits will carry valid audio data. the 12 trailing bits are set to zero by default. 2.11.6. parallel input/output interface (pio) the parallel interface of the mas 3587f consists of the 8 data lines pi12...pi19 (msb) and the control lines pcs , pr, prtr , prtw , and eod . it can be used for data exchange with an external memory and for other special purposes as defined by the dsp software. the pio interface is always used for mpeg-data out- put. for the handshake protocol please refer to section 4.6.3.7. for mpeg-data input, the pio interface is activated by setting bits 9,8 in d0:7f1 to 01. for the handshake pro- tocol please refer to section 4.6.3.6. advance information mas 3587f micronas 15 2.12. mpeg synchronization output the signal at pin sync is set to ? 1 ? after the internal decoding for the mpeg header has been finished for one frame. the rising edge of this signal can be used as an interrupt input for the controller that triggers the read out of the control information and ancillary data. as soon as the mas 3587f has received the sync reset command (see section 3.3.1.12. ), the sync signal is cleared. if the controller does not issue a reset command, the sync signal returns to ? 0 ? as soon as the decoding of the next mpeg frame is started. mpeg status and ancillary data become invalid until the frame is completely decoded and the signal at pin sync rises again. the controller must have finished reading all mpeg information before it becomes invalid. the mpeg layer2/3 frame lengths are given in table 2 ? 2. fig. 2 ? 10: schematic timing of the signal at pin sync. the signal is cleared at t read when the controller has issued a clear sync signal command (see section 3.3.1.12. ). if no command is issued, the signal returns to ? 0 ? just before the decoding of the next mpeg frame. 2.13. default operation this sections refers to the standard operation mode ? power-optimized solution ? (see section 2.9.3.). 2.13.1. stand-by functions after applying the battery voltage, the system will remain stand-by, as long as the dcen pin level is kept low. due to the low stand-by current of cmos circuits, the battery may remain connected to dcson/vsensn at all times. 2.13.2. power-up of the dc/dc converters and reset the battery voltage must be applied to pin dcson via the 22-h inductor and, furthermore, to the sense pin vsensn via a schottky diode (see fig. 2 ? 7 on page 12). for start-up, the pin dcen must be connected via an external ? start ? push button to the i2cvdd supply, which is equivalent to the battery supply voltage (> 0.9 v) at start-up. the supply at dcen must be applied until the dc/dc converters have started up (signal at pin pup) and then removed for normal operation. as soon as the output voltage at vsensn reaches the default voltage monitor reset level of 3.0 v, the respec- tive internal pupn bit will be set. when both pupn bits are set, the signal at pin pup will go high and can be used to start and reset the microcontroller. before transmitting any i 2 c commands, the controller must issue a power-on reset to pin por . the separate supply pin i2cvdd assures that the i 2 c interface works indepentently of the dsp or the audio codec. now the desired supply voltage can be programmed at i 2 c subaddress 76 hex (see table 3 ? 3 on page 20). the signal at pin pup will return to low only when both pupn flags (i 2 c subaddress 76 hex ) have returned to zero. care must be taken when changing both dc/dc output voltages to higher values. in this case, both out- put voltages are momentarily insufficient to keep the pupn flags up; the resulting dip in the signal at the pup pin may in turn reset the microcontroller. to avoid this condition, only one dc/dc output voltage should be changed at a time. before modifying the second voltage, the microcontroller must wait for the pupn flag of the first voltage to be set again. the operating mode (pulse width modulation or pulse frequency modulation, synchronized rectifier for higher efficiency) are controlled at i 2 c subaddress 76 hex , the operating frequency at i 2 c subaddress 77 hex . table 2 ? 2: frame length in mpeg layer 2/3 f s /khz frame length layer 2 frame length layer 3 48 24 ms 24 ms 44.1 26.12 ms 26.12 ms 32 36 ms 36 ms 24 24 ms 24 ms 22.05 26.12 ms 26.12 ms 16 36 ms 36 ms 12 not available 48 ms 11.025 not available 52.24 ms 8 not available 72 ms v h v l t read t frame = 24...72 ms mas 3587f advance information 16 micronas 2.13.3. control of the signal processing before starting the dsp, the controller should check for a sufficient voltage supply (respective flag pupn at i 2 c subaddress 76 hex ). the dsp is enabled by setting the appropriate bit in the control register (i 2 c subaddress 6a hex ). the nominal frequency of the crystal oscillator must be written into d0:7f3. after an initialization phase of 5 ms, the dsp data registers can be accessed via i 2 c (see table 3 ? 3 on page 20). input and output control is performed via memory loca- tion d0:7f1 and d0:7f2. the parallel interface (pio) is the default setting for compressed data. the decoded audio can be routed to either the spdif, the sdo and the analog outputs. the output clock signal at pin clko is defined in d0:7f4. the specific settings for audio encoding are written to memory location d0:7f0 (continued). all changes in the d0-memory cells become effective synchronously upon setting the lsb of main i/o con- trol (see table 3 ? 7 on page 34). the common way to start encoding or decoding is to perform all necessary settings and switch on the appli- cation by selecting the desired bit(s) in the application selection memory cell (d0:7f6) (see table 3 ? 6 on page 33). the digital volume control (see table 3 ? 7 on page 34) is applied to the output signal of the dsp. the decoded audio data is by default available at the spdif 1 output interface (for mpeg 1 sampling frequencies). the dsp does not have to be started if its functions are not needed, e.g. for routing audio via the a/d and the d/a converters through the codec part of the ic. 2.13.4. start-up of the audio codec (see table 3 ? 3 on page 20) before enabling the audio codec, the controller should check for a sufficient voltage supply (respective flag pupn at i 2 c subaddress 76 hex ). the audio codec is enabled by setting the appropriate bit at the control register (i 2 c subaddress 6a hex ). after an initialization phase of 5 ms, the dsp data registers can be accessed via i 2 c. the a/d and the d/a con- verters must be switched on explicitly (00 00 hex at i 2 c subaddress 6c hex ). the d/a converters may either accept data from the a/d converters or the output of the dsp, or a mix of both (register 00 06 hex and 00 07 hex at i 2 c subaddress 6c hex ). finally, an appropriate output volume (00 10 hex at i 2 c subaddress 6c hex ) must be selected. 2.13.5. power-down (see table 3 ? 3 on page 20) all analog outputs should be muted and the a/d and the d/a converters must be switched off (register 00 10 hex and 00 00 hex at i 2 c subaddress 6c hex ). the dsp and the audio codec must be disabled (clear dsp_en and codec_en bits in the control register, i 2 c subaddress 6a hex ). by clearing both dc/dc enable flags in the control register (i 2 c subaddress 6a hex ), the microcontroller can power down the com- plete system. advance information mas 3587f micronas 17 3. i 2 c interface 3.1. general 3.1.1. device address controlling the mas 3587f is done via an i 2 c slave interface. the device addresses are 3c/3e hex (device write) and 3d/3f hex (device read) as shown in table 3 ? 1. the device address pair 3c/3d hex applies if the dvs pin is connected to vss, the device address pair 3e/ 3f hex applies if the dvs pin is connected to vdd. i 2 c clock synchronization is used to slow down the interface if required. 3.1.2. i 2 c registers and subaddresses the interface uses one level of subaddresses. the mas 3587f interface has 7 subaddresses allocated for the corresponding i 2 c registers. the registers can be divided into three categories as shown in table 3 ? 2. the address 6a hex is used for basic control, i.e. reset and task select. the other addresses are used for data transfer from/to the mas 3587f. the i 2 c registers of the mas 3587f are 16 bits wide, the msb is denoted as bit[15]. transmissions via i 2 c bus have to take place in 16-bit words (two byte trans- fers, msb sent first); thus, for each register access, two 8-bit data words must be sent/received via i 2 c bus. table 3 ? 1: i 2 c device address a7 a6 a5 a4 a3 a2 a1 w/r 001111dvs0/1 table 3 ? 2: i 2 c subaddresses sub- address (hex) i 2 c- register name function direct configuration 6a con- trol controller writes to mas 3587f control register 76 dccf controller writes to first dc/dc configuration regis- ter 77 dcfr controller writes to second dc/dc config reg. dsp core access 68 data (write) controller writes to mas 3587f dsp 69 data (read) controller reads from mas 3587f dsp codec access 6c codec (write) controller writes to mas 3587f codec register 6d codec (read) controller reads from mas 3587f codec register mas 3587f advance information 18 micronas 3.1.3. naming convention the description of the various controller commands uses the following formalism: ? abbreviations used in the following descriptions: a address d data value n count value o offset value r register number x don ? t care ? a data value is split into 4-bit nibbles which are num- bered beginning with 0 for the least significant nib- ble. ? data values in nibbles are always shown in hexa- decimal notation. ? a hexadecimal 20-bit number d is written, e.g. as d = 17c63 hex , its five nibbles are d0 = 3 hex , d1 = 6 hex , d2 = c hex , d3 = 7 hex , and d4 = 1 hex . ? variables used in the following descriptions: i 2 c address: dw 3c/3e hex dr 3d/3f hex dsp core: data_write 68 hex data_read 69 hex codec: codec_write 6c hex codec_read 6d hex ? bus signals sstart pstop aack = acknowledge n nak = not acknowledge w wait = i2c clockline is held low, while the mas 3587f is processing the i2c command ? symbols in the telegram examples < start condition > stop dd data bytes xx ignore all telegram numbers are hexadecimal, data origi- nating from the mas 3587f are greyed. example: advance information mas 3587f micronas 19 3.2. direct configuration registers the task selection of the dsp and the dc/dc converters are controlled in the direct configuration registers control, dccf, and dcfr. 3.2.1. write direct configuration registers the write protocol for the direct configuration registers only consists of device address, subaddress and one 16-bit data word. 3.2.2. read direct configuration register to check the pup1 and pup2 power-up flags, it is necessary to read back the content of the direct configuration reg- isters. s subaddress d3,d2 a a a a dw d1,d0 p s subaddress a a dw p s subaddress d3,d2 a a a dw d1,d0 a 1) send subaddress 2) get register value s dr n p mas 3587f advance information 20 micronas table 3 ? 3: direct configuration registers i 2 c sub- address (hex) function name 6a control register (reset value = 3000 hex ) bit[15:14] analog supply voltage range code agndc recommended for voltage range of avdd 00 1.1 v 2.0 ... 2.4 v (reset) 01 1.3 v 2.4 ... 3.0 v 10 1.6 v 3.0 ... 3.6 v 11 reserved reserved higher voltage ranges permit higher output levels and thus a better signal-to- noise ratio. bit[13] enable dc/dc 2 (reset=1) bit[12] enable dc/dc 1 (reset=1) both dc/dc converters are switched on by default. bit[11] enable and reset audio codec bit[10] enable and reset dsp core for normal operation (mpeg-decoding and d/a conversion), both, the dsp core and the audio codec have to be enabled after the power-up procedure. the dsp can be left off if an audio signal is routed from the analog inputs to the analog outputs (set bit[15] in codec register 00 0f hex ). the audio codec can be left off if the dsp uses digital inputs and outputs only. bit[9] reset codec bit[8] reset dsp core bit[7] 1) reserved, must be set to zero bit[6:0] reserved, must be set to zero control 1) usage in the next version: enable xtal input clock divider (extended crystal range up to 28 mhz) advance information mas 3587f micronas 21 76 dccf register (reset = 5050 hex ) dccf dc/dc converter 2 bit[15] pup2: voltage monitor 2 flag (readback) bit[14:11] voltage between vsens2 and dcsg2 code nominal set level reset level output volt. of pup2 of pup2 1111 3.5 v 3.4 v 3.3 v 1110 3.4 v 3.3 v 3.2 v 1101 3.3 v 3.2 v 3.1 v 1100 3.2 v 3.1 v 3.0 v 1011 3.1 v 3.0 v 2.9 v 1010 3.0 v 2.9 v 2.8 v (reset) 1001 2.9 v 2.8 v 2.7 v 1000 2.8 v 2.7 v 2.6 v 0111 2.7 v 2.6 v 2.5 v 0110 2.6 v 2.5 v 2.4 v 0101 2.5 v 2.4 v 2.3 v 0100 2.4 v 2.3 v 2.2 v 0011 2.3 v 2.2 v 2.1 v 0010 2.2 v 2.1 v 2.0 v 0001 1) 2.1 v 2.0 v 1.9 v 0000 1) 2.0 v 1.9 v 1.8 v bit[10] mode 1 pulse frequency modulation (pfm) 0 pulse width modulation (pwm) (reset) bit[9] reserved, must be set to zero bit[8] disable synchronized rectifier 1 disable synchronized recitifier 0 enable synchronized recitifier (reset) the dc/dc converters are up-converters only. thus, if the battery voltage is higher than the selected nominal voltage, the output voltage will exceed the nominal voltage. 1) refer to section 4.6.2. on page 59 table 3 ? 3: direct configuration registers i 2 c sub- address (hex) function name mas 3587f advance information 22 micronas 76 (continued) dc/dc converter 1 bit[7] pup1: voltage monitor 1 flag (readback) bit[6:3] voltage between vsens1 and dcsg1 (see table above) bit[2] mode 1 pulse frequency modulation (pfm) 0 pulse width modulation (pwm) (reset) bit[1] reserved, must be set to zero bit[0] disable synchronized rectifier 1 disable synchronized recitifier 0 enable synchronized recitifier (reset) note, that the reference voltage for dc/dc converter 1 is derived from the main reference source supplied via pin avdd1. therefore, if this dc/dc con- verter is used, its output must be connected to the analog supply. the dc/dc converters are up-converters only. thus, if the battery voltage is higher than the selected nominal voltage, the output voltage will exceed the nominal voltage. table 3 ? 3: direct configuration registers i 2 c sub- address (hex) function name advance information mas 3587f micronas 23 77 dcfr register (reset = 00 hex )d c f r battery voltage monitor bit[15] comparison result (readback) 1 input voltage at pin vbat above defined threshold 0 input voltage at pin vbat below defined threshold bit[14] number of battery cells 0 1 cell (range 0.8...1.5 v) (reset) 1 2 cells (range 1.6...3.0 v) bit[13:10] voltage threshold level 1 cell 2 cells 1111 1.5 3.0 v 1110 1.45 2.9 v ... 0010 0.85 1.7 v 0001 0.8 1.6 v 0000 battery voltage supervision off (reset) bit[9:8] reserved, must be set to 0 the result is stable after 1 ms after enabling. the setup time for switching between two thresholds is negligibly small. for power management reasons, the battery voltage monitor should be switched off by setting bit[13:10] to zero when the measurement is completed. dc/dc converter frequency control (pwm) bit[7:4] reserved, must be set to 0 bit[3:0] frequency of dc/dc converter reference: 24.576 22.5792 18.432 mhz 0111 315.1 289.5 297.3 khz 0110 323.4 297.1 307.2 khz 0101 332.1 305.1 317.8 khz 0100 341.3 313.6 329.1 khz 0011 351.1 322.6 341.3 khz 0010 361.4 332.0 354.5 khz 0001 372.4 342.1 368.6 khz 0000 384.0 352.8 384.0 khz (reset) 1111 396.4 364.2 400.7 khz 1110 409.6 376.3 418.9 khz 1101 423.7 389.3 438.9 khz 1100 438.9 403.2 460.8 khz 1011 455.1 418.1 485.1 khz 1010 472.6 434.2 512.0 khz 1001 491.5 451.6 542.1 khz 1000 512.0 470.4 576.0 khz if the audio codec is not enabled (bit 11 of the control register at i 2 c-subad- dress 6a hex is zero), the clock for the dc/dc converters is directly derived from the crystal frequency (nominal 18.432 mhz). otherwise, the synthesizer clock is used as the reference (please refer to the respective column in ta b l e 2 ? 1 on page 10). table 3 ? 3: direct configuration registers i 2 c sub- address (hex) function name mas 3587f advance information 24 micronas 3.3. dsp core the dsp core of the mas 3587f has two ram banks denoted d0 and d1. the word size is 20 bits. all ram addresses can be accessed in a 20-bit or a 16-bit mode via i 2 c bus. for fast access of internal dsp states, the processor core also has an address space of 256 data registers. all register and ram addresses are given in hexadecimal notation. 3.3.1. access protocol the access of the dsp core in the mas 3587f uses a special command syntax. the commands are exe- cuted by the dsp during its normal operation without any loss or interruption of the incoming data or outgo- ing audio data stream. these i 2 c commands allow the controller accessing the internal dsp registers and ram cells and thus, monitoring internal states and set- ting the parameters for the dsp firmware. this access also provides a download option for alternative soft- ware modules. the mas 3587f firmware scans the i 2 c interface peri- odically and checks for pending or new commands. however, due to some time critical firmware parts, a certain latency time for the response has to be expected. the theoretical worst case response time does not exceed 4 ms. however, the typical response time is less than 0.5 ms. ta b l e 3 ? 4 gives an overview over the different com- mands which the dsp core receives via the i 2 c data register. the ? code ? is always the first data nibble transmitted after the ? data_write ? subaddress byte. a second auxiliary code nibble is used for the short memory (16-bit) access commands. due to the 16-bit width of the i 2 c data register, all actions transmit telegrams with multiples of 16 data bits. fig. 3 ? 2: general core access protocol s dw a w $68 aw code , ... a ... , ... a ... , ... table 3 ? 4: basic controller command codes code (hex) command function 0...3 run start execution of an internal program. run with start address 0 means freeze the operating system. 5 read ancillary data the controller reads a block of mpeg ancillary data from the mas 3587f 6 fast program download the controller downloads custom software via the pio interface a read from register the controller reads an internal register of the mas 3587f b write to register the controller writes an internal register of the mas 3587f c read d0 memory the controller reads a block of the dsp memory d read d1 memory the controller reads a block of the dsp memory e write d0 memory the controller writes a block of the dsp memory f write d1 memory the controller writes a block of the dsp memory advance information mas 3587f micronas 25 3.3.1.1. run and freeze the run command causes the start of a program part at address a = (a3,a2,a1,a0). since nibble a3 is also the com- mand code (see table 3 ? 4), it is restricted to values between 0 and 3. if the start address is 1000 hex a < 3fff hex and the respective ram area has been configured as program ram (see table 3 ? 5 on page 32), the mas 3587f continues execution with a custom program already downloaded to this area. example 1: start program execution at address 345 hex : mas 3587f advance information 26 micronas 3.3.1.3. write register (code b hex ) the controller writes the 20-bit value ( d = d4,d3,d2, d1,d0) into the mas 3587f register ( r =r1,r0). example: writing the value 81234 hex into the register with the number aa hex : advance information mas 3587f micronas 27 3.3.1.5. short read d0 memory (code c4 hex ) because most cells in the user interface are only 16 bits wide, it is faster and more convenient to access the memory locations with a special 16 bit mode for reading: this command is similar to the normal 20 bit read command and uses the same command code c hex , however it is followed by a 4 hex rather than a 0 hex . 3.3.1.6. read d1 memory (code d hex ) the read d1 memory command is provided to get information from d1 memory cells of the mas 3587f. s dw a w $69 aw s dw a w $68 aw c ,4 a 0,0 aw d3,d2 a d1,d0 aw 2) get memory value s dr a w 1) send command n3,n2 a n1,n0 aw a3,a2 a a1,a0 aw p d3,d2 a d1,d0 nw p ...repeat for n data values... s dw a w $69 aw s dw a w $68 aw d ,0 a 0,0 aw d3,d2 a d1,d0 aw 2) get memory value s dr a w 1) send command n3,n2 a n1,n0 aw a3,a2 a a1,a0 aw p p ...repeat for n data values... x,x a x,d4 w a d3,d2 a d1,d0 nw x,x a x,d4 w a mas 3587f advance information 28 micronas 3.3.1.7. short read d1 memory (code d4 hex ) the short read d1 memory command works similar to the read d1 memory command but with the code d hex fol- lowed by a 4 hex . example: read 16 bits of d1:123 has the following i 2 c protocol: advance information mas 3587f micronas 29 3.3.1.9. short write d0 memory (code e4 hex ) for faster access only the lower 16 bits of each memory cell are accessed. the 4 msbs of the cell are cleared. 3.3.1.10. write d1 memory (code f hex ) for further details, see the write d0 memory command. 3.3.1.11. short write d1 memory (code f4 hex ) only the 16 lower bits of each memory cell are written, the upper 4 bits are cleared. s dw a w $68 aw e ,4 a 0,0 aw n3,n2 a n1,n0 aw d3,d2 a d1,d0 aw ...repeat for n data values... d3,d2 a d1,d0 aw p a3,a2 a a1,a0 aw s dw a w $68 aw f ,0 a 0,0 aw n3,n2 a n1,n0 aw d3,d2 a d1,d0 aw ...repeat for n data values... 0,0 a 0,d4 aw d3,d2 a d1,d0 aw p 0,0 a 0,d4 aw a3,a2 a a1,a0 aw s dw a w $68 aw f ,4 a 0,0 aw n3,n2 a n1,n0 aw d3,d2 a d1,d0 aw ...repeat for n data values... d3,d2 a d1,d0 aw p a3,a2 a a1,a0 aw mas 3587f advance information 30 micronas 3.3.1.12. clear sync signal (code 5 hex ) after the successful decoding of an mpeg frame the signal at pin sync rises and thus generates an interrupt event for the microcontroller. issuing this command lets the signal at pin sync return to ? 0 ? . 3.3.1.13. default read the default read command is the fastest way to get information from the mas 3587f. executing the default read in a polling loop can be used to detect a special state during decoding. the default read command immediately returns the lower 16 bit content of a specific ram location as defined by the pointer d0:ffb. the pointer must be loaded before the first default read action occurs. if the msb of the pointer is set, the pointer refers to a memory location in d1 rather than to one in d0. example: for watching d1:123 the pointer d0:ffb must be loaded with 8123 hex : advance information mas 3587f micronas 31 3.3.1.14. fast program download the fast program download command introduces a data transfer via the parallel port. n = n2,n1,n0 denotes the number of 20-bit data words to be transferred, a = a3,a2,a1,a0 gives the start address. the data at the pio port must be padded with three 0-nibbles to get multiples of 16 bits. the download must be initiated in the following sequence: ? issue freeze command ? stop all dma transfers ? issue fast program download command ? download code via pio interface ? switch appropriate memory area to act as program ram (register ed hex ) ? issue run command to start program execution at entry point of downloaded code example for fast program download command: download 4 words starting at d0:1400: (stop all data transfers) mas 3587f advance information 32 micronas 3.3.2. list of dsp registers ta b l e 3 ? 5 lists the registers used in the standard firmware (mpeg) and for the download option (download). note: registers not given in the tables must not be written. 3.3.3. list of dsp memory cells among the user interface control memory cells there are some which have a global meaning and some which control application specific parts of the dsp core. in the tables below this is reflected by the key- words all, encoder and decoder. 3.3.3.1. application select and running the appselect cell is a global user interface configura- tion cell, which has to be written in order to start a spe- cific application. the apprunning cell is a global user interface status cell, which indicates, which application loop is actually running. the meaning of the bits in both cells is given in table 3 ? 6. following steps have to be performed to switch between applications: ? write ? 0 ? to appselect ? check apprunning for ? 0 ? ? apply necessary/wanted control settings ? write value to appselect according to table 3 ? 6 3.3.3.2. application specific control the configuration of the mpeg encoder and decoder firmware is done via the control memory cells described in table 3 ? 7. the changes applied to any of the control memory cells have to be validated by set- ting bit[0] of memory cell main i/o control except when the application is started by writing the appselect memory cell. the validate bit will be reset automati- cally after the changes have been taken over by the dsp. the status memory cells are used to read the encoder/ decoder status and to get additional mpeg bitstream information. note: memory cells not given in the tables must not be written. table 3 ? 5: dsp register table address (hex) r/w functionmode default (hex) name 6b r/w configuration of variable ram areas download affected ram area bit[19] d0:800 ... d0:bff bit[18] d0:c00 ... d0:fff bit[17] d1:800 ... d1:bff bit[16] d1:c00 ... d1:fff this register is used to switch four ram areas from data to program usage and thus enabling the dsp ? s program counter to access downloaded program code stored at these locations. for normal operation (firmware in rom) this register must be kept to zero. for details of program code download please refer to section 3.3.1.14. 0000 pselect_shadow 56 r s/pdif 1) input channel status bits mpeg bit[15:0] channel status bits of incoming signal. 0000 spichannelstatus 1) iec 958 amendment1, ? digital audio interface ? advance information mas 3587f micronas 33 table 3 ? 6: application control and status memory address (hex) function name d0:7f6 application selection all appselect is used for selecting an application. this is done by setting the appropriate bit to one. it is principally allowed to set more than one bit to one, e.g. setting appselect to 0xc will select all mpeg audio decoders. the auto- detection feature will automatically detect the layer 2 or layer 3 data. when bit[0]/bit[1] are asserted, the dsp begins to loop inside the os loop/top level loop respectively. it is recomended to perform the necessary settings for the firmware before the application is started by writing this memory cell. bit[6] mpeg layer 3 encoder bit[3] mpeg layer 3 decoder bit[2] mpeg layer 2 decoder bit[1] top level bit[0] operating system appselect d0:7f7 application running all the apprunning cell is a global user interface status cell, that indicates which application loop is actually running. after writing appselect, it has to be checked whether the appropriate bit(s) in the apprunning cell is set, prior to any changes in the configuration registers or memory cells bit[6] mpeg layer 3 encoder bit[3] mpeg layer 3 decoder bit[2] mpeg layer 2 decoder bit[1] top level bit[0] operating system apprunning d0:7f0 encoder control (reset = a0264 hex ) encoder encodercontrol is used for selecting the quality level, sample frequency and other options for encoding. bit[19:17] quality setting 000 0 lowest bitrate / quality 001 1 010 2 011 3 100 4 101 (reset) 5 recommended quality the maximum bitrate is limited to 192 kbit/s, whereas the average bitrate highly depends on the audio source. at the recommanded quality setting and a sampling rate of 44.1 khz, the average bitrate is typically found in the range from 130 to 140 kbit/s. 110 6 111 7 highest bitrate / quality bit[16:12] reserved, must be set to zero ... encodercontrol mas 3587f advance information 34 micronas table 3 ? 7: d0 control memory cells memory address (hex) function name d0:7f0 (continued) bit[11:10] sampling frequency (khz) mpeg 1 mpeg 2 00 (reset) 44.1 22.05 01 48 24 10 32 16 11 reserved bit[9] mpeg selection 0m p e g 2 1 (reset) mpeg 1 bit[11:9] are only evaluated for sdi audio input (selected in d0:7f1, bit[9:8]). in case of s/pdif audio input, mpeg 1 is used and the sampling frequency is auto detected. bit[8] crc protection 0 (reset) enable crc protection 1 disable crc protection bit[7:6] channel mode 00 reserved 01 (reset) joint stereo 10 reserved 11 single channel bit[5] channel mode extension (for joint stereo) 0 disable ms-stereo encoding 1 (reset) enable ms-stereo encoding bit[4] reserved, must be set to zero bit[3] copyright 0 (reset) bit stream is not copyright protected 1 bit stream is copyright protected bit[2] copy / original 0 bit stream is a copy 1 (reset) bit stream is an original bit[1:0] emphasis 00 (reset) none 01 50/15 s 10 reserved 11 ccitt j.17 advance information mas 3587f micronas 35 d0:7f1 main i/o control (reset = 124 hex ) all iocontrolmain is used for selecting/deselecting the appropriate data input interface and for setting up the serial data output interface. in serial input mode the coded audio data (layer 2, layer 3) is expected at the serial input interface sdib. in the 8-bit-parallel input mode (default) the pio pins pi[19:12] are used. bit[15] reserved, must be set to zero bit[14] invert serial output clock (soc) 0 (reset) do not invert soc 1invert soc bit[13:12] reserved, must be set to zero bit[11] serial data output delay 0 (reset) no additional delay (reset) 1 additional delay of data related to word strobe bit[10] reserved, must be set to zero bit[9:8] encoder: audio input select 00 sdi input with pll 01 (reset) sdi input without pll 10 s/pdif input 11 reserved decoder: data input select 00 serial input at interface b 01 (reset) parallel input at pio pins pi[19...12] 10 reserved 11 reserved bit[7] encoder: invert serial input clock (sic) 0 (reset) do not invert sic 1invert sic bit[6] encoder: serial data input delay 0 (reset) no additional delay (reset) 1 additional delay of data related to word strobe bit[5] sdo word strobe invert 0do not invert 1 (reset) invert outgoing word strobe signal bit[4] bits per sample at sdo 0 (reset) 32 bits/sample 1 16 bits/sample bit[3] encoder: clock setting 0 (reset) mpeg 1 1mpeg2 bit[3] may only be set for mpeg 2 encoding. bit[2] serial data input interface b clock invert (pin sibc) 0 not inverted (data latched at rising clock edge) 1 (reset) incoming clock signal is inverted (data latched at falling clock edge) ... iocontrolmain table 3 ? 7: d0 control memory cells memory address (hex) function name mas 3587f advance information 36 micronas d0:7f1 (continued) main i/o control, continued bit[1] decoder: 0 (reset) demand mode (pll off, mas 3587f is clock master) 1 broadcast mode (pll on, clock of mas 3587f locks on data stream) encoder: sdi word strobe invert 0 (reset) do not invert 1 invert incoming word strobe signal note: l/r channel swap is present today with the reset value. correct value for encoder is ? 1 ? . correct default channel setting will be implemented in future versions. bit[0] validate 0 (reset) changes in control memory will be ignored 1 changes in control memory will become effective bit[0] is reset after the dsp has recognized the changes. the controller should set this bit after the other d0 control memory cells have been initialized with the desired values. d0:7f2 interface status control (reset = 05 hex ) all this control cell allows to enable/disable the data i/o interfaces. in addition, the clock of the output data interfaces, s/pdif and sdo, can be set to a low- impedance mode. bit[6] s/pdif input selection 0 (reset) select s/pdif input 1 1 select s/pdif input 2 bit[5] enable/disable s/pdif output 0 (reset) enable s/pdif output 1 s/pdif output off (tristate) note that s/pdif audio output is only available for mpeg 1 (sampling fre- quencies 32, 44.1 and 48 khz) bit[4] reserved, must be set to zero bit[3] enable/disable serial data output sdo 0sdo on 1 (reset) sdo off bit[2] output clock characteristic (sdo and s/pdif outputs) 0 low impedance 1 (reset) high impedance bit[1] reserved, must be set to zero bit[0] enable/disable external serial data input sdi 0 use external audio source (sdi) 1 (reset) use internal a/d converter as audio source both digital outputs, s/pdif and spo, and the d/a converters may use the outgoing audio independent of each other. changes at this memory address must be validated by setting bit [0] of d0:7f1. interfacecontrol table 3 ? 7: d0 control memory cells memory address (hex) function name advance information mas 3587f micronas 37 d0:7f3 oscillator frequency (reset = 18432 dec ) all bit[19:0] oscillator frequency in khz in order to achieve a correct internal operating frequency of the dsp, the nom- inal crystal frequency has to be deposited into this memory cell. changes at this memory address must be validated by setting bit 0 of d0:7f1. ofreqcontrol d0:7f4 output clock configuration (pin clko) (reset = 80000 hex ) all bit[19] clko configuration 0 output clock signal at clko 1 (reset) clko is tristate the clko output pin of the mas 3587f can be disabled via bit [19]. bit[18] reserved, must be set to zero bit[17] additional division by 2 if scaler is on (bit[8] cleared) 0 (reset) oversampling factor 512/768 1 oversampling factor 256/384 bit[16:9] reserved, must be set to zero bit[8] output clock scaler 0 (reset) set output clock according to audio sample rate (see table 2 ? 1) 1 output clock fixed at 24.576 or 22.5792 mhz for a list of output frequencies at pin clko please refer to table 2 ? 1. bit[7:0] reserved, must be set to zero changes at this memory address must be validated by setting bit[0] of d0:7f1. outclkconfig d0:7f8 s/pdif 1) channel status bits category code setting (reset = 8004 hex ) all spdoutbits d0:7f9 soft mute (reset = 0 hex ) decoder bit[19:0] 0 (reset) mute off 1 mute on softmute d0:7fc volume output control: left left gain (reset = 80000 hex ) decoder out_ll d0:7fd volume output control: left right gain (reset = 0 hex ) decoder out_lr d0:7fe volume output control: right left gain (reset = 0 hex ) decoder out_rl d0:7ff volume control: right right gain (reset = 80000 hex ) decoder out_rr 1) iec 958 amendment1, ? digital audio interface ? table 3 ? 7: d0 control memory cells memory address (hex) function name mas 3587f advance information 38 micronas table 3 ? 8: d0 status memory cells memory address function name d0:fd0 mpeg frame counter all bit[19:0] number of mpeg frames after synchronization the counter will be incremented with every new frame that is encoded/ decoded. with an invalid mpeg bit stream at its input while decoding (e.g. an invalid header is detected), the mas 3587f resets the mpegframecount to ? 0 ? . in encoding mode, the counter is reset on audio data timeouts and after restarting the encoder. mpegframecount d0:fd1 mpeg header and status information all bit[15] reserved, must be set to zero bit[14:13] mpeg id, bits 12, 11 of the mpeg header 00 mpeg 2.5 (decoding only) 01 reserved 10 mpeg 2 11 mpeg 1 bit[12:11] bits 14 and 13 of the mpeg header 00 reserved 01 layer 3 10 layer 2 (decoding only) 11 layer 1 (decoding only) bit[10] crc protection 0 bitstream protected by crc 1 bitstream not protected by crc bit[9:2] reserved bit[1] crc error (decoding only) 0 no crc error 1 crc error bit[0] invalid frame (decoding only) 0 no invalid frame 1 invalid frame this location contains bits 15...11 of the original mpeg header and other sta- tus bits. it will be set each frame directly after the header has been encoded/ decoded from the bit stream. mpegstatus1 advance information mas 3587f micronas 39 d0:fd2 mpeg header information all bit[15:12] mpeg layer 2/3 bitrate mpeg1, l2 mpeg1, l3 mpeg2, l2/3 0000 free free free 0001 32 32 8 0010 48 40 16 0011 56 48 24 0100 64 56 32 0101 80 64 40 0110 96 80 48 0111 112 96 56 1000 128 112 64 1001 160 128 80 1010 192 160 96 1011 224 192 112 1100 256 224 128 1101 320 256 144 1110 384 320 160 1111 forbidden forbidden forbidden bit[11:10] sampling frequencies in hz mpeg1 mpeg2 mpeg2.5 00 44100 22050 11025 01 48000 24000 12000 10 32000 16000 8000 11 reserved reserved reserved bit[9] padding bit bit[8] reserved bit[7:6] mode 00 stereo 01 joint_stereo (intensity stereo / m/s stereo) 10 dual channel 11 single channel bit[5:4] mode extension (applies to joint stereo only) intensity stereo m/s stereo 00 off off 01 on off 10 off on 11 on on bit[3] copyright protect bit 0/1 not copyright protected/copyright protected bit[2] copy/original bit 0/1 bitstream is a copy/bitstream is an original ... mpegstatus2 table 3 ? 8: d0 status memory cells memory address function name mas 3587f advance information 40 micronas 3.3.4. ancillary data the memory fields d0:fd5...d0:ff1 contain the ancil- lary data. it is organized in 28 words of 16 bit each. the last ancillary bit of a frame is placed at bit 0 in d0:fd5. the position of the first ancillary data bit received can be located via the content of numbero- fancillarybits because int[(numberofancillarybits-1)/16] + 1 of memory words are used. example: first get the content of ? numberofancillarybits ? advance information mas 3587f micronas 41 3.3.5. dsp volume control the digital baseband volume matrix is used for control- ling the digital gain of the decoder as shown in fig. 3 ? 3. this volume control is effective on both, the digital audio output and the data stream to the d/a convert- ers. the values are in 20-bit 2 ? s complement notation. ta b l e 3 ? 9 shows the proposed settings for the 4 vol- ume matrix coefficients for stereo, left and right mono. the gain factors are given in fixed point notation ( ? 1.0 2 19 = 80000 hex ). the dsp volume control is available in decoder mode only. fig. 3 ? 3: digital volume matrix if channels are mixed, care must be taken to prevent clipping at high amplitudes. therefore the sum of the absolute values of coefficients for one output channel should be less than 1.0. for normal operating conditions it is recommended to use the main volume control of the audio codec instead (register 00 10 hex of the audio codec). ? 1 ? 1 ? 1 ? 1 ll lr rl rr + + left audio right audio from mpeg decoder to digital output and d/a table 3 ? 9: settings for the digital volume matrix memory d0:354 d0:355 d0:356 d0:357 name ll lr rl rr stereo (default) ? 1.0 0 0 ? 1.0 mono left ? 1.0 ? 1.0 0 0 mono right 0 0 ? 1.0 ? 1.0 table 3 ? 10: content of d0:fd5 after reception of 19 ancillary bits. d0:fd5 msb 14 13 12 11 10 9 8 7 6 5 4 3 2 1 lsb ancillary data 4th bit 5th bit 6th bit ... ... ... ... ... ... ... ... ... ... 17th bit 18th bit last bit table 3 ? 11: content of d0:fd6 after reception of 19 ancillary bits. d0:fd6 msb 14 13 12 11 10 9 8 7 6 5 4 3 2 1 lsb ancillary data xxxxxxxxxxxxxfirst bit 2nd bit 3rd bit mas 3587f advance information 42 micronas 3.4. audio codec access protocol the mas 3587f has 16-bit wide registers for the control of the audio codec. these registers are accessed via the i 2 c subaddresses codec_write (6c hex ) and codec_read (6d hex ). 3.4.1. write codec register the controller writes the 16-bit value ( d = d3,d2,d1,d0) into the mas 3587f codec register ( r = r3,r2,r1,r0). a list of registers is given in table 3 ? 12. example: writing the value 1234 hex into the codec register with the number 00 1b hex : advance information mas 3587f micronas 43 3.4.3. codec registers table 3 ? 12: codec control registers on i 2 c subaddress 6c hex register address (hex) function name converter configuration 00 00 audio codec configuration 0 db is related to the d/a full-scale output voltage (please refer to section 4.6.4. on page 72) bit[15:12] a/d converter left amplifier gain = n*1.5 ? 3 [db] bit[11:8] a/d converter right amplifier gain = n*1.5 ? 3 [db] 1111 +19.5 db 1110 +18.0 db ... ... 0011 +1.5 db 0010 0.0 db 0001 ? 1.5 db 0000 ? 3.0 db bit[7:4] microphone amplifier gain = n*1.5+21 [db] 1111 +43.5 db 1110 +42.0 db ... ... 0001 +22.5 db 0000 +21.0 db bit[3] input selection for left a/d converter channel 0 line-in 1 microphone bit[2] enable left a/d converter 1) bit[1] enable right a/d converter 1) bit[0] enable d/a converter 1) conv_conf 1) the generation of the internal dc reference voltage for the d/a converter is also controlled with this bit. in order to avoid click noise, the reference voltage at pin agndc should have reached a near ground potential before repower- ing the d/a converter after a short down phase. alternatively at least one of the a/d converters (bits [2] or [1]) should remain set during short power-down phases of the d/a. then the dc reference volt- age generation for the d/a converter will not be interrupted. input mode select 00 08 input mode setting bit[15] mono switch 0 stereo input mode 1 left channel is copied into the right channel bit[14:2] reserved, must be set to 0 bit[1:0] deemphasis select 0 deemphasis off 1 deemphasis 50 s 2 deemphasis 75 s adc_in_mode mas 3587f advance information 44 micronas output mode select 00 06 00 07 d/a converter source mixer mix adc scale mix dsp scale bit[15:8] 00 hex ... 7f hex linear scaling factor (hex) for example: 00 hex off 20 hex 50 % ( ? 6db gain) 40 hex 100 % (0 db gain) 7f hex 200% (+6db gain) in the sum of both mixing inputs exceeds 100 %, clipping may occur in the successive audio processing. dac_in_adc dac_in_dsp 00 0e d/a converter output mode bit[15] mono switch 0 stereo through 1 mono matrix applied bit[14] invert right channel 0 through 1 right channel is inverted bit[1:0] reserved, must be set to 0 in order to achieve more output power a single loudspeaker can be connected as a bridge between pins outl and outr. in this mode bit[15] and bit[14] must be set. dac_out_mode baseband features 00 14 bass bit[15:8] bass range 60 hex + 12 db 58 hex + 11 db ... 08 hex + 1db 00 hex 0db f8 hex ? 1db ... a8 hex ? 11 db a0 hex ? 12 db higher resolution is possible, one lsb step results in a gain step of about 1/8 db. with positive bass settings clipping of the output signal may occur. therefore, it is not recommended to set bass to a value that, in conjunction with volume, would result in an overall positive gain. the settings require: max (bass, treble) + loudness + volume 0db bit[7:0] not used, must be set to 0 bass table 3 ? 12: codec control registers on i 2 c subaddress 6c hex register address (hex) function name advance information mas 3587f micronas 45 00 15 treble bit[15:8] treble range 60 hex + 12 db 58 hex + 11 db ... 08 hex + 1db 00 hex 0db f8 hex ? 1db ... a8 hex ? 11 db a0 hex ? 12 db higher resolution is possible, one lsb step results in a gain step of about 1/8 db. with positive treble settings, clipping of the output signal may occur. there- fore, it is not recommended to set treble to a value that, in conjunction with loudness and volume, would result in an overall positive gain. the settings require: max (bass, treble) + loudness + volume 0db bit[7:0] not used, must be set to 0 treble 00 1e loudness bit[15:8] loudness gain 44 hex + 17 db 40 hex + 16 db ... 04 hex + 1db 00 hex 0db bit[7:0] loudness mode 00 hex normal (constant volume at 1 khz) 04 hex super bass (constant volume at 2 khz) higher resolution of loudness gain is possible: an lsb step results in a gain step of about 1/4 db. loudness increases the volume of low- and high-frequency signals, while keeping the amplitude of the 1-khz reference frequency constant. the intended loudness has to be set according to the actual volume setting. because loudness introduces gain, it is not recommended to set loudness to a value that, in conjunction with volume, would result in an overall positive gain. the settings should be: max (bass, treble) + loudness + volume 0db the corner frequency for bass amplification can be set to two different values. in super bass mode, the corner frequency is shifted up. the point of constant volume is shifted from 1 khz to 2 khz. ldness table 3 ? 12: codec control registers on i 2 c subaddress 6c hex register address (hex) function name mas 3587f advance information 46 micronas micronas dynamic bass (mdb) 00 22 mdb effect strength bit[15:8] 00 hex mdb off (default) 7f hex maximum mdb the mdb effect strength can be adjusted in 1db steps. a value of 40 hex will yield a medium mdb effect. mdb_str 00 23 mdb harmonics bit[15:8] 00 hex no harmonics are added (default) 64 hex 50% fundamentals + 50% harmonics 7f hex 100% harmonics the mdb exploits the psychoacoustic phenomenon of the ? missing fundamen- tal by creating harmonics of the frequencies below the center frequency of the bandpass filter (mdb_fc). this enables a loudspeaker to display frequencies that are below its cutoff frequency. the variable mdb_har describes the ratio of the harmonics towards the original signal. mdb_har 00 24 mdb center frequency bit[15:8] 2 20 hz 330hz ... 30 300 hz the mdb center frequency defines the center frequency of the mdb band- pass filter (see fig. 3 ? 4 on page 49). the center frequency should approxi- mately match the cutoff frequency of the loudspeakers. for high end loudspeakers, this frequency is around 50 hz, for low end speakers around 90 hz mdb_fc 00 21 mdb shape bit[15:8] 5...30 corner frequency in 10-hz steps (range: 50...300 hz) with a second lowpass filter the steepness of the falling slope of the mdb bandpass can be increased (see fig. 3 ? 4 on page 49). choosing the corner frequency of this filter close to the center frequency of the bandpass filter (mdb_fc) results in a narrow mdb frequency range. the smaller this range, the harder the bass sounds. the recommended value is around 1.5 mdb_fc mdb_shape mdb switch bit[7:2] reserved, must be set to zero bit[1] mdb switch 0mdb off 1mdb on bit [0] reserved, must be set to zero mdb_switch table 3 ? 12: codec control registers on i 2 c subaddress 6c hex register address (hex) function name advance information mas 3587f micronas 47 volume 00 10 volume control bit[15:8] volume table with 1 db step size 7f hex + 12 db (maximum volume) 7e hex + 11 db ... 74 hex + 1db 73 hex 0db 72 hex ? 1db ... 02 hex ? 113 db 01 hex ? 114 db 00 hex mute (reset) bit[7:0] not used, must be set to 0 this main volume control is applied to the analog outputs only. it is split between a digital and an analog function. in order to avoid noise due to large changes of the setting, the actual setting is internally low-pass filtered. with large scale input signals, positive volume settings may lead to signal clip- ping. volume 00 11 balance bit[15:8] balance range 7f hex left ? 127 db, right 0 db 7e hex left ? 126 db, right 0 db ... 01 hex left ? 1db, right 0db 00 hex left 0 db, right 0 db ff hex left 0 db, right ? 1db ... 81 hex left 0 db, right ? 127 db 80 hex left 0 db, right ? 128 db positive balance settings reduce the left channel without affecting the right channel; negative settings reduce the right channel leaving the left channel unaffected. balance 00 12 automatic volume correction (avc) loudspeaker channel bit[15:12] 0 hex avc off (and reset internal variables) 8 hex avc on bit[11:8] 8 hex 8 s decay time 4 hex 4 s decay time 2 hex 2 s decay time 1 hex 20 ms decay time (intended for quick adaptation to the average volume level after track or source change) note: to reset the internal variables, the avc should be switched off and then on again during any track or source change. for standard applications, the recommended decay time is 4 s. avc table 3 ? 12: codec control registers on i 2 c subaddress 6c hex register address (hex) function name mas 3587f advance information 48 micronas table 3 ? 13: codec status registers on i 2 c subaddress 6d hex register address (hex) function name input quasi-peak 00 0a a/d converter quasi-peak detector readout left bit[14:0] positive 15-bit value, linear scale 0000 0% 2000 25% ( ? 12 dbfs) 4000 50% ( ? 6dbfs) 7fff 100% (0 dbfs) qpeak_l 00 0b a/d converter quasi-peak detector readout right bit[14:0] positive 15-bit value, linear scale 0000 0% 2000 25% ( ? 12 dbfs) 4000 50% ( ? 6dbfs) 7fff 100% (0 dbfs) qpeak_r output quasi-peak 00 0c audio processing input quasi-peak detector readout left bit[14:0] positive 15-bit value, linear scale dqpeak_l 00 0d audio processing input quasi-peak detector readout right bit[14:0] positive 15-bit value, linear scale dqpeak_r advance information mas 3587f micronas 49 3.4.4. basic mdb configuration with the parameters described in table 3 ? 12, the mic- ronas dynamic bass system (mdb) can be custom- ized to create different bass effects as well as to fit the mdb to various loudspeaker characteristics. the easi- est way to find a good set of parameter is by selecting one of the settings below, listening to music with strong bass content and adjusting the mdb parameters: ? mdb_str: increase/decrease the strength of the mdb effect ? mdb_har: increase/decrease the content of low frequency harmonics ? mdb_fc: shift the mdb effect to lower/higher fre- quencies ? mdb_shape: widen/narrow mdb frequency range (which results in a softer/harder bass sound), turn on/off the mdb fig. 3 ? 4: micronas dynamic bass (mdb): bass boost in relation to input signal leve frequency mdb_fc signal level amplitude (db) mdb_shape table 3 ? 14: suggested mdb settings function mdb_str (22 hex ) mdb_har (23 hex ) mdb_fc (24 hex ) mdb_shape (21 hex ) mdb off xxxx hex xxxx hex xxxx hex 0000 hex low end headphones, medium effect 5000 hex 3000 hex 0600 hex 0902 hex mas 3587f advance information 50 micronas 4. specifications 4.1. outline dimensions fig. 4 ? 1: 64-pin plastic low-profile quad flat pack (plqfp64) weight approximately 0.35 g dimensions in mm 4.2. pin connections and short descriptions nc not connected, leave vacant lv if not used, leave vacant x obligatory, pin must be connected as described in application information (see fig. 4 ? 30 on page 79) vdd connect to positive supply vss connect to ground 10 0.1 1.75 1.75 49 64 116 17 32 33 48 d0025/3e 0.5 0.5 0.1 12 0.2 1.5 0.1 1.4 0.05 12 0.2 10 0.1 0.145 0.055 0.22 0.05 15 x 0.5 = 7.5 0.1 15 x 0.5 = 7.5 0.1 pin no. plqfp 64-pin pin name type default connection (if not used) short description 1 agndc x analog reference voltage 2 micin in lv input for internal microphone amplifier 3 micbi in lv bias for internal microphone 4 inl in lv left a/d input 5 inr in lv right a/d input 6 te in x test enable 7 xti in x crystal oscillator (ext. clock) input 8 xto out lv crystal oscillator output 9por in x power on reset, active low 10 vss supply x dsp supply ground 11 xvss supply x digital output supply ground 12 vdd supply x dsp supply advance information mas 3587f micronas 51 13 xvdd supply x digital output supply 14 i2cvdd supply x i 2 c supply 15 dvs in x i 2 c device address selector 16 vsens1 in/out vdd sense input and power output of dc/dc 1 converter 17 dcso1 supply lv dc/dc 1 switch output 18 dcsg1 supply vss dc/dc 1 switch ground 19 dcsg2 supply vss dc/dc 2 switch ground 20 dcso2 supply lv dc/dc 2 switch output 21 vsens2 in/out vdd sense input and power output of dc/dc 2converter 22 dcen in vss dc/dc enable (both converters) 23 clko out lv clock output 24 i2cc in/out x i 2 c clock 25 i2cd in/out x i 2 c data 26 sync out lv sync output 27 vbat in lv battery voltage monitor input 28 pup out lv dc converter power-up signal 29 eod out lv pio end of dma, active low 30 prtr out lv pio ready to read, active low 31 prtw out lv pio ready to write, active low 32 pr in vdd pio dma request, active high 33 pcs in vss pio chip select, active low 34 pi19 in/out lv pio data bit 7 (msb) 35 pi18 in/out lv pio data bit 6 36 pi17 in/out lv pio data bit 5 37 pi16 in/out lv pio data bit 4 38 pi15 in/out lv pio data bit 3 39 pi14 in/out lv pio data bit 2 40 pi13 in/out lv pio data bit 1 41 pi12 in/out lv pio data bit 0 (lsb) 42 sod out lv serial output data pin no. plqfp 64-pin pin name type default connection (if not used) short description mas 3587f advance information 52 micronas 43 soi out lv serial output frame identification 44 soc out lv serial output clock 45 sid in vss serial input data, interface a 46 sii in vss serial input frame identification, inter- face a 47 sic in vss serial input clock, interface a 48 spdo out lv s/pdif output interface 49 sibd in vss serial input data, interface b 50 sibc in vss serial input clock, interface b 51 sibi in vss serial input frame identification, inter- face b 52 spdi2 in lv active differential s/pdif input 2 53 spdi1 in lv active differential s/pdif input 1 54 spdir in lv reference differential s/pdif input 1 and 2 55 filtl in x feedback input for left amplifier 56 avdd0 supply x analog supply for output amplifiers 57 outl out lv left analog output 58 outr out lv right analog output 59 avss0 supply x analog ground for output amplifiers 60 filtr in x feedback for right output amplifier 61 avss1 supply x analog ground 62 vref x analog reference ground 63 pvdd supply x internal power supply 64 avdd1 supply x analog supply pin no. plqfp 64-pin pin name type default connection (if not used) short description advance information mas 3587f micronas 53 4.3. pin descriptions 4.3.1. power supply pins the use of all power supply pins is mandatory to achieve correct function of the mas 3587f. vdd, vss supply digital supply pins. xvdd, xvss supply supply for digital output pins. i2cvdd supply supply for i 2 c interface circuitry. this net uses vss or xvss as the ground return line. pvdd supply auxiliary pin for analog circuitry. this pin has to be connected via a 3-nf capacitor to avdd1. extra care should be taken to achieve a low inductance pcb line. avdd0/avss0 supply supply for analog output amplifier (output stage). avdd1/avss1 supply supply for internal analog circuits (a/d, d/a convert- ers, clock, pll, s/pdif input). avdd0/avss0 and avdd1/avss1 should receive the same supply voltages. 4.3.2. analog reference pins agndc internal analog reference voltage. this pin serves as the internal ground connection for the analog circuitry. vref analog reference ground. all analog inputs and out- puts should drive their return currents using separate traces to a ground starpoint close to this pin. connect to avss1. this reference pin should be as noise free as possible. 4.3.3. dc/dc converters and battery voltage supervision dcsg1/dcsg2 supply dc/dc converters switch ground. connect using sepa- rate wide trace to negative pole of battery cell. con- nect also to avss0/1 and vss/xvss. dcso1/dcso2 supply dc/dc converter switch connection. if the respective dc/dc converter is not used, this pin must be left vacant. vsens1/vsens2 in sense input and power output of dc/dc converters. if the respective dc/dc converter is not used, this pin should be connected to a supply. dcen in enable signal for both dc/dc converters. if none of the dc/dc converters is used, this pin must be con- nected to vss. pup out power-up. this signal is set when the required volt- ages are available at both dc/dc converter output pins vsens1 and vsens2. the signal is cleared when both voltages have dropped below the reset level in the dccf register. vbat in analog input for battery voltage supervision. 4.3.4. oscillator pins and clocking xti in xto out the xti pin is connected to the input of the internal crystal oscillator, the xto pin to its output. each pin should be directly connected to the crystal and to a ground-connected capacitor (see application diagram). clko out the clko can drive an output clock line. 4.3.5. control lines i2cc scl in/out i2cd sda in/out standard i 2 c control lines. dvs in i 2 c device address selector. connect this pin either to vdd (i 2 c device address: 3e/3f hex ) or vss (i 2 c device address: 3c/3d hex ) to select a proper i 2 c device address (see also table 3 ? 1 on page 17). 4.3.6. parallel interface lines pi12..pi19 in/out the pio input pins pi12..pi19 are used as 8-bit i/o interface to a microcontroller in order to transfer com- pressed and uncompressed data. pi12 is the lsb, pi19 the msb. mas 3587f advance information 54 micronas 4.3.6.1. pio handshake lines pcs in the pio chip select pcs must be set to ? 0 ? to activate the pio in operation mode. pr in pin pr must be set to ? 1 ? when ready to send/receive data to/from mas 3587f pio pins. prtr out ready to read. this signal indicates that the mas 3587f is able to receive data in pio input mode. prtw out ready to write. this pin indicates that mas 3587f has data available in pio output mode. eod out eod indicates the end of an dma cycle in the ic ? s pio input/output mode. in ? serial ? input mode it is used as demand signal, that indicates that new input data are required. 4.3.7. serial input interface (sdi) sid data in sii word strobe in sic clock in i 2 s compatible serial interface a for digital audio data. this interface can be used for audio input in the encoder. 4.3.8. serial input interface b (sdib) sibd data in sibi word strobe in sibc clock in the serial interface b is used as bitstream input inter- face. the sibi line must be connected to vss in the serial decoder application. 4.3.9. serial output interface (sdo) sod data out soi word strobe out soc clock in/out data, frame indication, and clock line of the serial out- put interface. the sdo is reconfigurable and can be adapted to several i 2 s compliant modes. 4.3.10. s/pdif input interface spdi1 in spdi2 in spdir in spdif1 and spdif2 are alternative input pins for s/pdif sources according to the iec 958 consumer specification. a switch at d0:7f2 selects one of these pins at a time. the spdir pin is a common reference for both input lines (see fig. 4 ? 31 on page 80). 4.3.11. s/pdif output interface spdo out the spdo pin provides an digital output with standard cmos level that is compliant to the iec 958 consumer specification. 4.3.12. analog input interfaces the analog inputs are used in the standard mpeg encoding dsp firmware. they can also be selected as a source for the d/a converters (refer to audio codec register 00 07 hex (see table 3 ? 12 on page 43)). micin in micbi in the micin input may be directly used as electret microphone input, which should be connected as described in application information. the micbi signal provides the supply voltage for these microphones. inl in inr in inl and inr are analog line-in input lines. they are connected to the embedded stereo a/d converter of the mas 3587f. the sources should be ac coupled. the reference ground for these analog input pins is the vref pin. 4.3.13. analog output interfaces outl out outr out outl and outr are left and right analog outputs, that may be directly connected to built-in 16 ? loudspeak- ers via 22 ? series resistance to the headphones as described in the application information (see fig. 4 ? 30 on page 79). filtl in filtr in connection to input terminal of output amplifier.can be used to connect a capacitance from outl respectively outr to filtl respectively filtr in parallel to feed- back resistor and thus implement a low pass filter to reduce the out-of-band noise of the dac. advance information mas 3587f micronas 55 4.3.14. miscellaneous sync out the sync signal indicates the detection of a frame start in the input data of mas 3587f. usually this sig- nal generates an interrupt in the controller. por in the power-on reset pin is used to reset the whole mas 3587f, except for the dc/dc converter circuitry. por is an active-low signal. te in the te pin is for production test only and must be con- nected with vss in all applications. 4.4. pin configurations fig. 4 ? 2: plqfp64 package (top view) sibd sibc sibi spdi2 spdi1 spdir filtl avdd0 outl outr avss0 filtr avss1 vref pvdd avdd1 pr prtw prtr eod pup vbat sync i2cd i2cc clko dcen vsens2 dcso2 dcsg2 dcsg1 dcso1 sic sii sid soc soi sod pi12 spdo pi13 pi14 pi15 pi16 pi17 pi18 pi19 pcs micin micbi inl inr te xti xto agndc por vss xvss vdd xvdd i2cvdd dvs vsens1 mas 3587f 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10111213141516 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 mas 3587f advance information 56 micronas 4.5. internal pin circuits fig. 4 ? 3: input pins pcs , pr fig. 4 ? 4: input pin te, dvs, por fig. 4 ? 5: input pin dcen fig. 4 ? 6: input/output pins soc, soi, sod, pi12...pi19, spdo fig. 4 ? 7: input pins si(b)c, si(b)i, si(b)d fig. 4 ? 8: input/output pins i2cc, i2cd fig. 4 ? 9: input/output pins dcso1/2, dcsg1/2, vsens1/2 fig. 4 ? 10: output pins prtw , eod , prtr , clko, sync, pup fig. 4 ? 11: clock oscillator xti, xto ttlin xvdd p n xvss xvdd p n xvss vdd n vss dcso dcsg vsens n p xvdd xvss n p avdd avss p p p n n n xto xti enable advance information mas 3587f micronas 57 fig. 4 ? 12: analog input pins micin, inl, inr fig. 4 ? 13: microphone bias pin (micbi) fig. 4 ? 14: analog outputs outl(r) and connections for filter capacitors filtl(r) fig. 4 ? 15: analog ground generation with pin to connect external capacitor fig. 4 ? 16: s/pdif inputs fig. 4 ? 17: battery voltage monitor vbat ? + agndc a d micin inl inr micbi + agndc vref ? d a ? + agndc filtl(r) outl(r) i 1.25 v ? + agndc vref xvdd bias ? + xvdd spdi1, spdir spdi2 vss ? + vbat vss = programmable mas 3587f advance information 58 micronas 4.6. electrical characteristics 4.6.1. absolute maximum ratings stresses beyond those listed in the ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions beyond those indicated in the ? recommended operating conditions/characteristics ? of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. symbol parameter pin name min. max. unit t a ambient operating temperature ? 40 85 c t s storage temperature ? 40 125 c p tot power dissipation vdd, xvdd, avdd0/1, i2cvdd 650 mw v supa analog supply voltages 1) avdd0/1 ? 0.3 6 v v sup digital supply voltage vdd, xvdd, i2cvdd ? 0.3 6 v v ii2c input voltage, i 2 c-pins i2cc, i2cd ? 0.3 6 v v idig input voltage, all digital inputs ? 0.3 v sup +0.3 v i idig input current, all digital inputs ? 20 +20 ma v iana input voltage, all analog inputs ? 0.3 v sup + 0.3 v i iana input current, all analog inputs ? 5+ 5m a i oaudio output current, audio output 2) outl/r ? 0.2 0.2 a i odig output current, all digital outputs 3) ? 50 +50 ma i odcdc1 output current dcdc converter 1 dcso1 1.5 a i odcdc2 output current dcdc converter 2 dcso2 1.5 a 1) both avdd0 and avdd1 have to be connected together! 2) these pins are not short-circuit proof! 3) total chip power dissipation must not exceed absolute maximum rating advance information mas 3587f micronas 59 4.6.2. recommended operating conditions symbol parameter pin name min. typ. max. unit temperature range 1 and supply voltages t a1 ambient temperature range 1 ? 40 85 c v supd1 digital supply voltage (mpeg decoder) vdd, xvdd 2.2 2.5 3.9 v v supd2 digital supply voltage (mpeg 1 encoder) 3.5 3.9 digital supply voltage (mpeg 2 encoder) 2.7 3.9 v supi2c i 2 c bus supply voltage i2cvdd v supdn 1) at vdd 3.9 v v supa analog audio supply voltage avdd0/1 2.2 2.7 3.9 v analog audio supply voltage in relation to the digital supply volt- age 0.62 1.6 v supd v supx pin supply voltage in relation to digital supply voltage xvdd 0.62 1.6 v supd 1) n=1,2 table 4 ? 1: reference frequency generation and crystal recommendation symbol parameter pin name min. typ. max. unit external clock input recommendations f clk clock frequency xti, xto 13.00 18.432 20.00 mhz v clki clockamplitude of external clock fed into xti at v avdd =2.2v xti 0.7 1.05 v pp clockamplitude of external clock fed into xti at v avdd =2.7v 0.55 1.5 clockamplitude of external clock fed into xti at v avdd =3.3v 0.45 1.75 clockamplitude of external clock fed into xto at v avdd =2.2v xto 1.25 2.2 clockamplitude of external clock fed into xto at v avdd =2.7v 0.75 2.7 clockamplitude of external clock fed into xto at v avdd =3.3v 0.55 3.3 duty cycle xti, xto 455055% mas 3587f advance information 60 micronas crystal recommendations f p load resonance frequency at c i =20pf xti, xto 18.432 mhz ? f/f s accuracy of frequency adjust- ment ? 50 50 ppm ? f/f s frequency variation vs. temper- ature ? 50 50 ppm r eq equivalent series resistance 12 30 ? c 0 shunt (parallel) capacitance 3 5 pf table 4 ? 2: input levels symbol parameter pin name min. typ. max. unit i il input low voltage at v dd = 2.5...3.9 v i2cc, i2cd 0.3 v i ih input high voltage at v dd = 2.5...3.9 v 1.4 v i il input low voltage at v dd = 2.5...3.9 v por , dcen 0.2 v i ih input high voltage at v dd = 2.5...3.9 v 0.9 v i ild input low voltage pi, si(b)i, si(b)c, si(b)d, pr, pcs , te, dvs 0.3 v i ihd input high voltage v sup ? 0.5 v table 4 ? 1: reference frequency generation and crystal recommendation symbol parameter pin name min. typ. max. unit advance information mas 3587f micronas 61 table 4 ? 3: analog input and output recommendations symbol parameter pin name min. typ. max. unit analog reference c agndc1 analog filter capacitor agndc 1.0 3.3 f c agndc2 ceramic capacitor in parallel 10 nf c pvdd capacitor for analog circuitry pvdd 3 nf analog audio inputs c inad dc-decoupling capacitor at a/d- converter inputs inl/r 390 nf c inmi dc-decoupling capacitor at microphone-input micin 390 nf c lmicbi minimum-capacitance at micro- phone bias micbi 3.3 nf analog audio filter outputs c filt filter capacitor for headphone amplifier high-q type, np0 or c0g material filtl/r outl/r ? 20 % 470 +20 % pf analog audio output z aol_hp analog output load with stereo headphones outl/r 16 ? 100 pf dc/dc-converter external circuitry (please refer to application example) c 1 vsens blocking (<100 m ? esr) vsens1/2 330 f v th schottky diode threshold voltage dcso1/2 vsens1/2 0.35 v l ferrite ring core coil inductance dcso1/2 22 h s/pdif interface analog input c spi s/pdif coupling capacitor spdi1/2 spdir 100 nf mas 3587f advance information 62 micronas 4.6.3. digital characteristics at t a = t a2 , v supdn , v supa = 2.5 ... 3.6 v, f crystal = 18.432 mhz, typ. values for t a = 25 c symbol parameter pin name min. typ. max. unit test conditions digital supply voltage i supd1 current consumption (mpeg decoding) vdd, xvdd, i2cvdd 39 ma 2.5 v, sampling frequency 32 khz 20 2.5 v, sampling frequency 24 khz 11 2.5 v, sampling frequency 12 khz i supd2 current consumption (mpeg encoding) 145 3.5 v, sampling frequency 32 khz 70 2.7 v, sampling frequency 24 khz i standby total current at stand-by 10 a dsp off, codec off, dc /dc off, a/d and d/ac off, no i 2 c access digital outputs and inputs o digl output low voltage pi, soi, soc, sod, eod , prtr , prtw , clko, sync, pup, spdo 0.3 v i load = 2 ma o digh output low voltage v supd ? 0.3 vi load = ? 2ma z digi input impedance all digital inputs 7 pf i dleak digital input leakage current ? 11a0v < v pin < v supd advance information mas 3587f micronas 63 4.6.3.1. i 2 c characteristics at t a =25 c, v supi2c = 2.5...3.6 v fig. 4 ? 18: i 2 c timing diagram symbol parameter pin name min. typ. max. unit test conditions i 2 c input specifications f i2c upper limit i 2 c bus frequency operation i2cc 400 khz t i2c1 i 2 c start condition setup time i2cc, i2cd 300 ns t i2c2 i 2 c stop condition setup time i2cc, i2cd 300 ns t i2c3 i 2 c clock low pulse time i2cc 1250 ns t i2c4 i 2 c clock high pulse time i2cc 1250 ns t i2c5 i 2 c data setup time before rising edge of clock i2cc 80 ns t i2c6 i 2 c data hold time after falling edge of clock i2cc 80 ns v i2col i 2 c output low voltage i2cc, i2cd 0.4 v i load = 3 ma i i2coh i 2 c output high leakage current i2cc, i2cd 1a t i2col1 i 2 c data output hold time after falling edge of clock i2cc, i2cd 20 ns t i2col2 i 2 c data output setup time before rising edge of clock i2cc, i2cd 250 ns f i2c = 400 khz v i2cil i 2 c input low voltage i2cc; i2cd 0.3 v supi2c v i2cih i 2 c input high voltage i2cc, i2cd 0.6 v supi2c t w wait time i2cc, i2cd 00.54ms i2cc i2cd as input i2cd as output t i2c1 t i2c5 t i2c6 t i2c2 t i2c4 t i2c3 1/f i2c t i2col2 t ic2ol1 h l h l h l mas 3587f advance information 64 micronas 4.6.3.2. serial (i 2 s) input interface characteristics (sdi, sdib) at t a = t a2 , v supd , v supa = 2.5 ... 3.6 v, f crystal = 18.432 mhz, typ. values for t a = 25 c symbol parameter pin name min. typ. max. unit test conditions t siclk i 2 s clock input clock period si(b)c 325 ns f s =48khz stereo, 32 bits per sample (for demand mode see ta bl e 4 ? 4) t sids i 2 s data setup time before rising edge of clock (for continuous data stream: falling edge) si(b)c, si(b)d 50 ns t sidh i 2 s data hold time si(b)d 50 ns t siis i 2 s ident setup time before rising edge of clock (for continuous data stream: falling edge) si(b)c, si(b)i 50 ns t siih i 2 s ident hold time si(b)i 50 ns t bw burst wait time si(b)c, si(b)d 480 table 4 ? 4: maximum demand clock frequency f sample (khz) f c (mhz) min. t siclk 48, 32 6.144 162 44.1 5.6448 177 24, 16 3.072 325 22.05 2.8224 354 12, 8 1.536 651 11.025 1.4112 708 advance information mas 3587f micronas 65 fig. 4 ? 19: continuous data stream at serial input a or b. in this mode, the word strobe si(b)i is not used and the data are read at the falling edge of the clock (bit 2 in d0:7f1 is set). fig. 4 ? 20: serial input of i 2 s signal h l h l h l t siclk t sidh t sids si(b)c si(b)i si(b)d h l h l h l t siclk t sidh t sids t siih t siis si(b)c si(b)i si(b)d mas 3587f advance information 66 micronas 4.6.3.3. serial output interface characteristics (sdo) at t a = t a2 , v supd , v supa = 2.5 ... 3.6 v, f crystal = 18.432 mhz, typ. values for t a = 25 c fig. 4 ? 21: serial output interface timing. symbol parameter pin name min. typ. max. unit test conditions t soclk i 2 s clock output frequency soc 325 ns f s =48khz stereo 32 bits per sample t soiss i 2 s word strobe delay time after falling edge of clock soc, soi 0n s t soodc i 2 s data delay time after falling edge of clock soc, sod 0n s h l h l h l t soclk t soiss t soiss t soodc soc soi sod advance information mas 3587f micronas 67 fig. 4 ? 22: sample timing of the sdo interface in 16 bit/sample mode. d0:7f1 settings are: bit 14 = 0 (soc not inverted), bit 11 = 1 (soi delay), bit 5 = 0 (word strobe not inverted), bit 4 = 1 (16 bits/sample). fig. 4 ? 23: sample timing of the sdo interface in 32 bit/sample mode. d0:7f1 settings are: bit 14 = 0 (soc not inverted), bit 11 = 0 (no soi delay), bit 5 = 1 (word strobe inverted), bit 4 = 0 (32 bits/sample). soc sod v h v l soi left 16-bit audio sample right 16-bit audio sample 15141312111098 76543210 13 12 11 10 9 8 76543210 15 14 v h v l v h v l 302928272625...76543210 31302928272625 76543210 left 32-bit audio sample right 32-bit audio sample soc sod soi v h v l v h v l v h v l .. ... 31 ... mas 3587f advance information 68 micronas 4.6.3.4. s/pdif input characteristics at t a = t a2 , v supd , v supa = 2.5 ... 3.6 v, f crystal = 18.432 mhz, typ. values for t a = 25 c. fig. 4 ? 24: timing of the s/pdif input symbol parameter pin name min. typ. max. unit test conditions v s signal amplitude spdi1, spdi2, spdir 200 500 1000 mv pp f s1 bi-phase frequency spdi1, spdi2, spdir 2.048 mhz 1000 ppm, f s = 48 khz f s2 bi-phase frequency spdi1, spdi2, spdir 2.822 mhz 1000 ppm, f s = 44.1 khz f s3 bi-phase frequency spdi1, spdi2, spdir 3.072 mhz 1000 ppm, f s = 32 khz t p bi-phase period spdi1, spdi2, spdir 326 ns at f s = 48 khz, (highest sampling rate) t r rise time spdi1, spdi2, spdir 06 5n sa t f s = 48 khz, (highest sampling rate) t f fall time spdi1, spdi2, spdir 06 5n sa t f s = 48 khz, (highest sampling rate) duty cycle spdi 40 50 60 % at bit value=1 and f s =48khz t h1,l1 spdi 81 163 ns minimum/maximum pulse duration with a level above 90 % or below 10 % and at f s =48khz t h0,l0 spdi 163 244 ns minimum/maximum pulse duration with a level above 90 % or below 10 % and at f s =48khz t p t r t f bit value = 1 bit value = 0 t h1 t l1 t h0 t l0 advance information mas 3587f micronas 69 4.6.3.5. s/pdif output characteristics at t a = t a2 , v supd , v supa = 2.5 ... 3.6 v, f crystal = 18.432 mhz, typ. values for t a = 25 c. fig. 4 ? 25: timing of the s/pdif output symbol parameter pin name min. typ. max. unit test conditions f s1 bi-phase frequency spdo 3.072 mhz f s = 48 khz f s2 bi-phase frequency spdo 2.822 mhz f s = 44.1 khz f s3 bi-phase frequency spdo 2.048 mhz f s = 32 khz t p bi-phase period spdo 326 ns at f s = 48 khz, (highest sampling rate) t r rise time spdo 0 2 ns c load =10pf t f fall time spdo 0 2 ns c load =10pf duty cycle spdo 50 % t h1,l1 spdo 163 ns minimum/maximum pulse duration with a level above 90 % or below 10 % and at f s =48khz t h0,l0 spdo 326 ns minimum/maximum pulse duration with a level above 90 % or below 10 % and at f s =48khz v s signal amplitude spdo v supd t p t r t f bit value = 1 bit value = 0 t h1 t l1 t h0 t l0 mas 3587f advance information 70 micronas 4.6.3.6. pio as parallel input interface: dma mode in decoding mode, the data transfer can be started after the eod pin of the mas 3587f is set to ? high ? . after verifying this, the controller signalizes the send- ing of data by activating the pr line. the mas 3587f responds by setting the rtr line to the ? low ? level. the mas 3587f reads the data pi[19:12] and sets rtr to low after rising edge of pr. after rtr is set to high, the mc sets pr to low. the next data word write oper- ation will be initialized again by setting the pr line via the controller. please refer to figure 4 ? 26 for the exact timing the procedure above will be repeated until the mas 3587f sets the eod signal to ? 0 ? which indicates that the transfer of one data block has been executed. subsequently, the controller should set pr to ? 0 ? , wait until eod rises again and then repeat the procedure to send the next block of data. the dma buffer is 15 bytes long. the buffer size is subject to change in the next version. . fig. 4 ? 26: handshake protocol for writing mpeg data to the pio-dma symbol pin name min. max. unit t st pr, eod 0.010 2000 s t r pr, rtr 40 160 ns t pd pr, pi[19:12] 120 480 ns t set pi[19:12] 160 ns t h pi[19:12] 160 ns t rtrq rtr 200 30000 ns t pr pr 480 ns t rpr pr, rtr 160 ns t eod pr, eod 40 160 ns t eodq eod 2.5 500 s eod pr rtr pi[19:12] high low high low high low high low t st t rpr t rtrq t set t h t r t pr t pd t eodq t eod byte 15 byte 1 mas 3509f latches the pio data advance information mas 3587f micronas 71 4.6.3.7. pio as parallel output interface: dma mode in encoding mode, the mas 3587f signals available data by setting the eod pin to ? high ? . after verifying this, the controller signalizes its capability to receive one byte of data by activating the pr line. the mas 3587f responds by setting the rtw line to the ? low ? level when the actual byte is set on the data lines pi[19:12]. after pr is set to ? low ? level, the rtw line is set to ? high ? again. the next data word write operation will be initialized again by setting the pr line via the controller. please refer to fig. 4 ? 27 on page 71 for the exact timing. the procedure above will be repeated until the mas 3587f sets the eod signal to ? 0 ? which indicates that the transfer of one data block has been executed. subsequently, the controller should set pr to ? 0 ? , wait until eod rises again and then repeat the procedure to receive the next block of data. the dma buffer is 15 bytes long. the buffer size is subject to change in the next version. in order to transfer the worst case data rate of 192 kbit/s, the controller must react sufficiently fast. the mean response times (t0, t3, t5) must be faster than 10 ms. due to internal buffering in the mas 3587f, this time can be expanded up to 4.8 ms once within each frame (see table 2 ? 2 on page 15) in any case. fig. 4 ? 27: handshake protocol for reading mpeg data from the pio-dma table 4 ? 5: pio output mode timing symbol pin min. max. unit t 0 eod , pr 0.010 2000 s t 1 pr, pi 110 310 ns t 2 pi, rtw 18 55 ns t 3 rtw , pr 18 ns t 4 pr, rtw 90 260 ns t 5 rtw , pr 35 ns t eod tbd tbd ns t eodq 2.5 ns eod pr rtw pi[19:12] high low high low high low high low t 0 t 3 t 2 t eodq t eod byte 15 byte 1 t 4 t 5 t 1 mas 3587f advance information 72 micronas 4.6.4. analog characteristics at t a = t a2 , v supd = 2.5...3.6 v, v supa = 2.2 ... 3.6 v, f crystal = 13...20 mhz, typical values at t a = 25 c and f crystal =18.432mhz symbol parameter pin name min. typ. max. unit test conditions analog supply i avdd current consumption analog audio avdd0/1 5 ma v supa = 2.2 v, mute i qosc current consumption crystal oscillator avdd0/1 200 a codec = off dsp = off dc/dc = on i standby 10 codec = off dsp = off dc/dc = off crystal oscillator v dcclk dc voltage at oscillator pins xti, xto 0.5 v supa v aclk clock amplitude 0.5 v supa ? 0.5 v pp if crystal is used c in input capacitance 3 pf r out output resistance xto 220 ? v supa =2.2v 125 v supa =2.7v 94 v supa =3.3v analog audio v ai analog line input clipping level (at minimum analog input gain,i.e. ? 3db) inl/r v pp v supa bits 15, 14 in reg. 6a hex 2.2 >2.2 v 00 2.6 >2.4 v 01 3.2 >3.0 v 10 v mi microphone input clipping level (at minimum analog input gain, i.e. +21 db) micin mv pp v supa bits 15,14 in reg. 6a hex 141 >2.0 v 00 167 >2.4 v 01 282 >3.0 v 10 advance information mas 3587f micronas 73 v ao1 analog output voltage ac outl/r r l 1k ? input=0 dbfs digital v supa bits 15, 14 in reg 6a hex at 0 db output gain 1.56 v pp >2.2 v 00 1.84 >2.4 v 01 2.27 >3.0 v 10 at +3 db output gain 2.20 v pp >2.2 v 00 2.60 >2.6 v 01 3.20 >3.2 v 10 dv ao1 deviation of dc-level at analog output for agndc- voltage outl/r ? 20 20 mv v ao2 analog output voltage ac outl/r r l is 16 ? headphone and 22 ? seriesresistor input=0 dbfs digital (see fig. 4 ? 31 on page 80) v supa bits 15, 14 in reg 6a hex at 0 db output gain 1.56 v pp >2.2 v 00 1.84 >2.4 v 01 2.27 >3.0 v 10 at +3 db output gain 2.00 v pp >2.2 v 00 2.40 >2.6 v 01 3.00 >3.2 v 10 r inai analog line input resistance inl/r 97 k ? at minimum analog input gain, i.e. ? 3db 20 at maximum analog input gain, i.e. +19.5 db 67 not selected r inmi microphone input resistance micin 94 k ? at minimum analog input gain, i.e. ? 21 db 8 at maximum analog input gain, i.e. +43.5 db 94 not selected r inao analog output resistance outl/r 6 ? analog gain=+3 db, input=0 dbfs digital snr ai signal-to-noise ratio of line input inl/r 74 db(a) bw = 20 hz...20 khz, analog gain=0 db, input 1khz at v ai ? 20 db symbol parameter pin name min. typ. max. unit test conditions mas 3587f advance information 74 micronas snr mi signal-to-noise ratio of microphone input micin 73 db(a) bw = 20 hz...20 khz, analog gain=+21 db, input 1khz at v mi ? 20 db thd ai total harmonic distortion of analog inputs inl/r micin 0,01 0.02 % bw = 20 hz...20 khz, analog gain = 0 db, resp. 24 db, input 1 khz at ? 3 dbfs=v ai ? 6db resp. v mi -6 db xtalk ai crosstalk attenuation left/right channel (analog inputs) inl/r micin 80 db f = 1 khz, sine wave, analog gain = 0 db, input = ? 3dbfs psrr ai power supply rejection ratio for analog audio inputs avdd0/1, inl/r micin 45 db 1 khz sine at 100 mv rms 20 db 100 khz sine at 100 mv rms audio output snr ao signal-to-noise ratio of analog output outl/r 94 db(a) r l 16 ? bw = 20 hz...20 khz, analog gain = 0 db input = -20 dbfs thd ao total harmonic distortion (headphone) outl/r for r l 16 ? plus 22 ? series resistor (see fig. 4 ? 31 on page 80) for r l 1k ? 0.03 0.003 0.05 0.01 % % lev muteao mute level outl/r ? 113 dbv a-weighted bw=20 hz...22khz , no digital input signal, analog gain=mute xtalk ao crosstalk attenuation left/right channel (headphone) outlr 80 db f=1 khz, sine wave, outl/r: r l 16 ? (see fig. 4 ? 31 on page 80) analog gain=0 db input=-3 dbfs psrr ao power supply rejection ratio for analog audio outputs avdd0/1 outl/r 70 db 1 khz sine at 100 mv rms 35 db 100 khz sine at 100mv rms v agndc analog reference voltage agndc v r l >> 10 m ?, referred to vref v supa bits 15, 14 in reg. 6a hex 1.1 >2.2 v 00 1.3 >2.4 v 01 1.6 >3.0 v 10 symbol parameter pin name min. typ. max. unit test conditions advance information mas 3587f micronas 75 v micbi bias voltage for microphone micbi v supa bits 15, 14 in reg. 6a hex 1.8 >2.2 v 00 2.13 >2.4 v 01 2.62 >3.0 v 10 r micbi source resistance micbi 180 ? i max maximum current microphone bias micbi av supa bits 15, 14 in reg. 6a hex 300 >2.2 v 00 symbol parameter pin name min. typ. max. unit test conditions mas 3587f advance information 76 micronas 4.6.5. dc/dc converter characteristics at t a = t a2 , v in = 1.2 v (unless otherwise noted), v outn = 3.0 v, f clk = 18.432 mhz, f sw = 384 khz, typ. values for t a = 25 c symbol parameter pin name min. typ. max. unit test conditions v in minimum start-up input voltage *0.9vi load 1ma, dccf = 5050 hex (reset) v in minimum operating input voltage dc1* dc2* 0.7 0.8 vi load = 50 ma, dccf = 5050 hex (reset) dc1* dc2* 1.1 1.2 vi load = 200 ma, dccf = 5050 hex (reset) v out programmable output voltage range vsensn 2.0 3.5 v voltage settings in dccf register (i 2 c subaddress 76 hex ) v otol output voltage tolerance vsensn 2.88 3.12 v i load =20ma t a = 25 c i load1 output current 1 battery cell vsensn 200 ma v in = 0.9...1.5 v, 330 f i load2 output current 2 battery cells 600 ma v in = 1.8...3.0 v, 330 f dv out / dv in /v out line regulation vsensn 0.8 %/v dv out / v out load regulation dc1 dc2 vsens1 vsens2 ? 1.7 ? 1.8 %i load = 20...200 ma, h max maximum efficiency ? 95 % v in = 2.4 v, v out =3.5v f switch switching frequency dcson 297 384 576 khz (see section 2.9.2. on page 11) f startup switching frequency during start-up dcson 250 khz vsensn < 1.9 v i suppfm1 supply current in pfm mode vsens1 75 a 1) i suppfm2 vsens2 135 i suppwm1 supply current in pwm mode vsens1 265 a vsensn 1) 2) i suppwm2 vsens2 325 i lnmax nmos switch current limit (low side switch) dcson, dcsgn 1a i lptoff pmos switch turnoff current (rectifier switch) dcson, vsensn 70 ma i leak leakage current dcson, dcsgn 0.1 at j = 25 c, converter off, i load =0 a 1) current into vsensn. vin > vout+ ? v; ( ? v 0.4 v); no dc/dc-converter regulation switching action present 2) add. current of oscillator at pin avdd0/1, (see section 4.6.4. on page 72) advance information mas 3587f micronas 77 4.6.6. typical performance characteristics fig. 4 ? 28: efficiency vs. load current efficiency vs. load current dcdc1 (v out =3.5v) efficiency (%) load current (a) 100 80 60 40 20 0 10 ? 4 10 ? 3 10 ? 2 10 ? 1 v in : 3.0 v 2.4 v 1.8 v pfm pwm 1 3.0 v 1.8 v efficiency vs. load current dcdc1 (v out =3.0v) efficiency (%) load current (a) 100 80 60 40 20 0 10 ? 4 10 ? 3 10 ? 2 10 ? 1 v in : 2.4 v 1.5 v 1.2 v pfm pwm 1 0.9 v 0.9 v 2.4 v efficiency vs. load current dcdc2 (v out =3.5v) efficiency (%) load current (a) 100 80 60 40 20 0 10 ? 4 10 ? 3 10 ? 2 10 ? 1 v in : 3.0 v 2.4 v 1.8 v pfm pwm 1 1.8 v 3 0 v efficiency vs. load current dcdc2 (v out =3.0v) efficiency (%) load current (a) 100 80 60 40 20 0 10 ? 4 10 ? 3 10 ? 2 10 ? 1 v in : 2.4 v 1.5 v 1.2 v pfm pwm 1 0.9 v 0.9 v 2.4 v mas 3587f advance information 78 micronas fig. 4 ? 29: maximum load current vs. input voltage note : efficiency is measured as v sensn i load /(v in i in ). i avdd is not included (oscillator current) efficiency vs. load current dcdc1 (v out =2.2v) efficiency (%) load current (a) 100 80 60 40 20 0 10 ? 4 10 ? 3 10 ? 2 10 ? 1 v in : 1.5 v 1.2 v 0.9 v pfm pwm 1 0.9 v 1.5 v maximum load current maximum load current (a) input voltage (v) 0.8 0.6 0.4 0.2 0 0.0 1.0 2.0 3.0 vs. input voltage v out : 2.2 v 3.0 v 3.5 v pfm pwm dcdc1 efficiency vs. load current dcdc2 (v out =2.2v) efficiency (%) load current (a) 100 80 60 40 20 0 10 ? 4 10 ? 3 10 ? 2 10 ? 1 v in : 1.5 v 1.2 v 0.9 v pfm pwm 1 0.9 v 1.5 v maximum load current maximum load current (a) input voltage (v) 0.8 0.6 0.4 0.2 0 0.0 1.0 2.0 3.0 vs. input voltage v out : 2.2 v 3.0 v 3.5 v pfm pwm dcdc2 advance information mas 3587f micronas 79 4.7. typical application in a portable player ? mmc/sdi-card or smc/cf2+ used as storage media ? dashed lines show optional (external) devices fig. 4 ? 30: application circuit of the mas 3587f. for connections of the dc/dc converters, please refer to fig. 4 ? 31. sibd sibc sibi spdi2 spdi1 spdir filtl avdd0 outl outr avss0 filtr avss1 vref pvdd avdd1 pr prtwq prtrq eodq pup vbat sync i2cd i2cc clko dcen vsens2 dcso2 dcsg2 dcsg1 dcso1 micin micbi inl inr te xti xto agndc porq vss xvss vdd xvdd i2cvdd dvs vsens1 mas 3587f 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 12345678910111213141516 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 pcsq pi19 pi18 pi17 pi16 pi15 pi14 pi13 pi12 sod soi soc sid sii sic spdo 470p 470p 3n 10n 22u 3u3 10n 100n 220p 1n 1.5u 4u7 18.432 mhz 1n 1.5u d a d a vdc2 18p 18p 5 4k7 4k7 vdc1 220u 220u 22 22 75 75 100 100 1.5k 1.5k 6.8n 6.8n a 100n 100n 390n 390n 390 n a 390p 390p 3.6...5.6 k mic lr headphone > 16 ? cd/dvd-player iec 958 iec 958 digiamp serial memory device e.g. sd-card 2 mpeg 3 3 8 i 2 s ? i/o parallel memory device e.g. s mart media c ard, pio-control mpeg see figure caption c vdc1 tape recorder fm radio vdc1 vdc1 vdc1 option for reference clock place vdd / xvdd -filter capacitors above ground plane 10k a d star point dcsg1 and dcsg2 ground connection d d d 10k place all cermic capacitors as close as possible to ic pins 470p capacitorss should be high-q (np0 or c0g) very close to pins i 2 c-address connect to vss or i2cvdd separate trace vdc1 vdc2 hard disk 3.3 n mas 3587f advance information 80 micronas 4.8. recommended dc/dc converter application circuit configuration 1 (see fig. 2 ? 8 on page 13) fig. 4 ? 31: external circuitry for the dc/dc converters mas 3587f v in (input voltage) vdc2 d2, schottky dcsg2 dcso2 l2 = 22 h dcen vsens2 e.g. 2.5 v/3.5 v (0.9..1.5 v) + power-on push button c2 = 330 f (low esr) vdc1 d1, schottky dcsg1 vss, xvss dcso1 l1 = 22 h vsens1 e.g. 2.7 v + c3 = 330 f (low esr) + c1 = 330 f vbat d avss0/1 a a d avdd0/1 very close to pins star point dcsg1 and dcsg2 ground connection v ref advance information mas 3587f micronas 81 all information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. any new issue of this data sheet invalidates previous issues. product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples deliv- ered. by this publication, micronas gmbh does not assume responsibil- ity for patent infringements or other rights of third parties which may result from its use. further, micronas gmbh reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. no part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of micronas gmbh. mas 3587f advance information 82 micronas micronas gmbh hans-bunte-strasse 19 d-79108 freiburg (germany) p.o. box 840 d-79008 freiburg (germany) tel. +49-761-517-0 fax +49-761-517-2174 e-mail: docservice@micronas.com internet: www.micronas.com printed in germany order no. 6251-542-1ai 5. data sheet history 1. advance information: ? mas 3587f mpeg layer 3 audio encoder/decoder ? , march 2, 2001, 6251-542-1ai. first release of the advance informa- tion. |
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